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1. 发明授权

US09806152B2 Vertical insulated gate turn-off thyristor with intermediate p+ layer in p-base 有权
公开(公告)号：US09806152B2
公开(公告)日：2017-10-31
申请号：US15448530
申请日：2017-03-02
申请人： Pakal Technologies, LLC
发明人： Hidenori Akiyama
IPC分类号： H01L29/00 , H01L29/10 , H01L29/745 , H01L29/423 , H01L29/74 , H01L29/744 , H01L29/66 , H01L29/78
CPC分类号： H01L29/102 , H01L29/0696 , H01L29/0839 , H01L29/41716 , H01L29/4236 , H01L29/66734 , H01L29/744 , H01L29/745 , H01L29/7455 , H01L29/7827 , H01L2924/1301 , H01L2924/1302 , H01L2924/13021 , H01L2924/13022
摘要： An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an n-layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. The p-well has an intermediate highly doped portion. When the gate regions are sufficiently biased, an inversion layer surrounds the gate regions, causing the effective base of the npn transistor to be narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter), the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-type base.

2. 发明申请

US20160071815A1 Spacer System For A Semiconductor Switching Device 有权
标题翻译：一种半导体开关器件的间隔系统
公开(公告)号：US20160071815A1
公开(公告)日：2016-03-10
申请号：US14940635
申请日：2015-11-13
申请人： ABB Technology AG
发明人： Thomas Stiasny
IPC分类号： H01L23/00
CPC分类号： H01L23/051 , H01L23/32 , H01L23/544 , H01L24/72 , H01L24/90 , H01L2223/54426 , H01L2924/1301 , H01L2924/13022 , H01L2924/1305 , H01L2924/13055 , H01L2924/00
摘要： A spacer system for a semiconductor switching device which is formed as a spacer ring and a plurality of insulating elements and supporting elements are arranged in an alternating manner around a circumference of the spacer ring. The insulating element includes a recess receiving a cathode gate connector element. The supporting element includes a projection receiving a spring system for damping while assembling the switching device. The switching device includes a substrate, a cathode pole piece, an anode pole piece, strain buffer plates and a gate ring. Further connector elements, are electrically connecting the cathode pole piece and the gate ring of the semiconductor switching device to an external circuit unit. The space between the connector elements is minimised in order to reduce the gate circuit impedance, thus enabling an increased maximum turn-off current and further allowing for the use of larger semiconductor switching devices for high power applications.
摘要翻译：用于半导体开关器件的间隔器系统，其形成为间隔环和多个绝缘元件和支撑元件，以交替的方式围绕隔离环的圆周布置。绝缘元件包括接收阴极栅极连接器元件的凹部。支撑元件包括突出部，该突起在组装开关装置时接收用于阻尼的弹簧系统。开关装置包括基板，阴极极片，阳极极片，应变缓冲板和栅极环。另外的连接器元件将阴极极片和半导体开关器件的栅极环电连接到外部电路单元。连接器元件之间的空间被最小化以便减小门电路阻抗，从而能够增加最大关断电流，并进一步允许使用较大的半导体开关器件用于大功率应用。

3. 发明申请

US20170256614A1 VERTICAL INSULATED GATE TURN-OFF THYRISTOR WITH INTERMEDIATE P+ LAYER IN P-BASE 有权
公开(公告)号：US20170256614A1
公开(公告)日：2017-09-07
申请号：US15448530
申请日：2017-03-02
申请人： Pakal Technologies, LLC
发明人： Hidenori Akiyama
IPC分类号： H01L29/10 , H01L29/423 , H01L29/74 , H01L29/745
CPC分类号： H01L29/102 , H01L29/0696 , H01L29/0839 , H01L29/41716 , H01L29/4236 , H01L29/66734 , H01L29/744 , H01L29/745 , H01L29/7455 , H01L29/7827 , H01L2924/1301 , H01L2924/1302 , H01L2924/13021 , H01L2924/13022
摘要： An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an p-layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. The p-well has an intermediate highly doped portion. When the gate regions are sufficiently biased, an inversion layer surrounds the gate regions, causing the effective base of the npn transistor to be narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter), the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-type base.

4. 发明授权

US09698067B2 Spacer system for a semiconductor switching device 有权
公开(公告)号：US09698067B2
公开(公告)日：2017-07-04
申请号：US14940635
申请日：2015-11-13
申请人： ABB Schweiz AG
发明人： Thomas Stiasny
IPC分类号： H01L23/051 , H01L23/32 , H01L23/00 , H01L23/544
CPC分类号： H01L23/051 , H01L23/32 , H01L23/544 , H01L24/72 , H01L24/90 , H01L2223/54426 , H01L2924/1301 , H01L2924/13022 , H01L2924/1305 , H01L2924/13055 , H01L2924/00
摘要： A spacer system for a semiconductor switching device which is formed as a spacer ring and a plurality of insulating elements and supporting elements are arranged in an alternating manner around a circumference of the spacer ring. The insulating element includes a recess receiving a cathode gate connector element. The supporting element includes a projection receiving a spring system for clamping while assembling the switching device. The switching device includes a substrate, a cathode pole piece, an anode pole piece, strain buffer plates and a gate ring. Further connector elements, are electrically connecting the cathode pole piece and the gate ring of the semiconductor switching device to an external circuit unit. The space between the connector elements is minimized in order to reduce the gate circuit impedance, thus enabling an increased maximum turn-off current and further allowing for the use of larger semiconductor switching devices for high power applications.

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