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11. 发明授权

US5846866A Drain extension regions in low voltage lateral DMOS devices 失效
标题翻译：在低压横向DMOS器件中漏极延伸区域
公开(公告)号：US5846866A
公开(公告)日：1998-12-08
申请号：US897278
申请日：1997-07-21
申请人： Robert Y. S. Huang , Monir El-Diwany
发明人： Robert Y. S. Huang , Monir El-Diwany
IPC分类号： H01L29/08 , H01L29/78 , H01L21/8224
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/7801
摘要： Disclosed are MOSFET devices in which a region extends from the drain and is, self-aligned with the gate. The region has a lower dopant concentration than the drain. The presence of the extension region substantially enhances breakdown voltage while not adding excessive on-resistance for the devices.
摘要翻译：公开了一种MOSFET器件，其中区域从漏极延伸并且与栅极自对准。该区域的掺杂浓度低于漏极。扩展区域的存在基本上增强了击穿电压，同时不会对器件增加过多的导通电阻。

12. 发明授权

US4415371A Method of making sub-micron dimensioned NPN lateral transistor 失效
标题翻译：制造亚微米尺寸的NPN横向晶体管的方法
公开(公告)号：US4415371A
公开(公告)日：1983-11-15
申请号：US220400
申请日：1980-12-29
申请人： Sidney I. Soclof
发明人： Sidney I. Soclof
IPC分类号： H01L21/8224 , H01L21/263 , H01L21/265 , H01L21/306 , H01L21/331 , H01L21/762 , H01L27/082 , H01L29/73 , H01L29/735 , H01L21/22 , H01L21/31
CPC分类号： H01L21/30608 , H01L21/2633 , H01L21/26586 , H01L21/76237 , H01L29/735
摘要： An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled motes or slotted regions, wherein the slots are utilized to dope the substrate within the action region. The N type substrate is double energy boron planted through one surface to establish a P region to a given depth. This surface is oxidized and photoresist masked conventionally to open regions for the slots which are ion milled or ODE etched to a given depth. N+ regions are established by the slots by ion implanting at an angle such that the entire depth of the slot is not doped but rather the doping is confined to a region within the double energy P implanted depth. Drive-in diffusion enlarges the N+ areas for the emitter and collecter and oxidation fills the mote insulating regions around the active area.The oxide is stripped and the P region enhanced to P+ at the surface, with silox being deposited and opened for metal contacts to the P+ region for the base and the emitter and collector regions. The doping profile of the base region provides a potential barrier to minimize the flow of electrons toward the surface because the emitter electrons are channeled through the less heavily doped part of the base region to the collector.
摘要翻译：通过为由场氧化物填充的微粒或开槽区域围绕的每个晶体管建立微小的有源区，可以在芯片上将数百个器件的阵列同时处理为亚微米尺寸，其中所述槽用于在衬底的作用区域内掺杂。 N型衬底是通过一个表面种植的双能硼，以建立到给定深度的P区。该表面被氧化并且光致抗蚀剂常规地掩蔽以打开用于离子研磨的槽的ODE或蚀刻到给定深度的ODE。通过离子注入以使角度的整个深度未掺杂的角度通过离子注入来建立N +区域，而是将掺杂限制在双能量P植入深度内的区域。驱动扩散扩大了发射器和收集器的N +面积，氧化填充了活动区域周围的微尘绝缘区域。氧化物被剥离，并且P区在表面增强至P +，其中silox被沉积并打开用于金属接触到用于基极和发射极和集电极区域的P +区域。基极区域的掺杂分布提供了一个势垒，以最小化电子朝向表面的流动，因为发射极电子通过基极区的较低掺杂部分被引导至集电极。

13. 发明授权

US4339767A High performance PNP and NPN transistor structure 失效
标题翻译：高性能PNP和NPN晶体管结构
公开(公告)号：US4339767A
公开(公告)日：1982-07-13
申请号：US146921
申请日：1980-05-05
申请人： Cheng T. Horng , Richard R. Konian , Robert O. Schwenker , Armin W. Wieder
发明人： Cheng T. Horng , Richard R. Konian , Robert O. Schwenker , Armin W. Wieder
IPC分类号： H01L21/331 , H01L21/762 , H01L21/8224 , H01L21/8228 , H01L27/082 , H01L29/10 , H01L29/423 , H01L29/73 , H01L29/732 , H01L29/735 , H01L27/02 , H01L29/04
CPC分类号： H01L29/66272 , H01L21/76202 , H01L21/76229 , H01L21/76232 , H01L21/8224 , H01L27/0821 , H01L29/1004 , H01L29/42304 , H01L29/7325 , H01L29/735
摘要： Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.
摘要翻译：公开了具有非常高的速度和低功率要求的PNP和NPN类型的非常小的集成电路器件的制造和结构。该结构提供了在同一半导体芯片内形成的垂直NPN和横向PNP晶体管。横向PNP晶体管的基极宽度非常窄（约300至400纳米）。这个窄尺寸部分通过使用明确定义的化学气相沉积（CVD）氧化物掩模而不是常规的光刻掩模来获得。为了消除注入衬底的发射极电流，PNP晶体管的P +发射极和P +集电极由氮化硅和二氧化硅介电层界定。

14. 发明授权

US4328509A Current hogging logic circuit with npn vertical reversal transistor and diode/pnp vertical transistor output 失效
标题翻译：具有npn垂直反向晶体管和二极管/ pnp垂直晶体管输出的当前ho逻逻辑电路
公开(公告)号：US4328509A
公开(公告)日：1982-05-04
申请号：US94119
申请日：1979-11-14
申请人： Heinz Lehning
发明人： Heinz Lehning
IPC分类号： H01L21/8224 , H01L21/331 , H01L27/082 , H01L29/73 , H01L29/735 , H03K19/088 , H03K19/091 , H03K23/00 , H01L29/72
CPC分类号： H03K19/091 , H01L29/735 , H03K23/002
摘要： In an n-type base island are provided a p-type emitter stripe and a p-type output collector stripe, with one or more intermediate control collector stripes for switching the current of the output collector. The pattern of control collector stripes can provide AND functions, OR functions or combinations thereof in a single logic element in a single base island. Each output is provided with an npn current reversal transistor in a separate island and if more than one input is to be operated by the output of a logic element, decoupling and fan-out capability are provided by vertical pnp transistors driven by the inverter transistors, which do not require an island completely separate from the inverter transistor, although an isolating barrier stripe can be helpful. A bistable flipflop and a frequency divider cell are shown to illustrate the use of these logic structures. The decoupling referred to can be provided without fan-out amplification by means of diodes.
摘要翻译：在n型基岛中设置有p型发射极条和p型输出集电极条，具有用于切换输出集电极的电流的一个或多个中间控制集电极条。控制收集器条纹的图案可以在单个基本岛中的单个逻辑元件中提供AND功能，OR函数或其组合。每个输出端在单独的岛中设置有npn电流反向晶体管，如果多个输入由逻辑元件的输出端操作，则由反相晶体管驱动的垂直pnp晶体管提供去耦和扇出能力，其不需要与逆变器晶体管完全分离的岛，尽管隔离屏障条可以是有帮助的。双稳态触发器和分频器单元被示出来说明这些逻辑结构的使用。可以通过二极管不提供扇出放大来提供所谓的去耦。

15. 发明授权

US3197710A Complementary transistor structure 失效
标题翻译：互补晶体管结构
公开(公告)号：US3197710A
公开(公告)日：1965-07-27
申请号：US28461163
申请日：1963-05-31
申请人： WESTINGHOUSE ELECTRIC CORP
发明人： CHANG LIN HUNG
IPC分类号： H01L21/76 , H01L21/8224 , H01L23/522 , H01L27/082
CPC分类号： H01L27/0821 , H01L21/76 , H01L21/8224 , H01L23/522 , H01L23/5227 , H01L2924/0002 , Y10S148/036 , Y10S148/053 , Y10S148/085 , Y10S148/096 , H01L2924/00

16. 发明授权

US11749672B2 Device for electrostatic discharge protection 有权
公开(公告)号：US11749672B2
公开(公告)日：2023-09-05
申请号：US17471190
申请日：2021-09-10
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Prantik Mahajan , Aloysius Priartanto Herlambang , Kyong Jin Hwang , Robert John Gauthier, Jr.
IPC分类号： H01L27/02 , H01L27/06 , H01L21/762 , H01L21/8224
CPC分类号： H01L27/0248 , H01L21/76202 , H01L21/76224 , H01L21/8224 , H01L27/067 , H01L27/0658 , H01L27/0664
摘要： A device includes a first region, a second region disposed on the first region, a third region and a fourth region abutting the third region disposed in the second region, a fifth region disposed in the third region and coupled to a collector disposed above, and a sixth region disposed in the fourth region and coupled to an emitter disposed above. A first isolation is disposed between the collector and the emitter. A seventh region is disposed in the fifth region and coupled to the collector is spaced apart from the first isolation. The first region, the third region, the fifth region, the collector and the emitter have a first conductivity type different from a second conductivity type that the second region, the fourth region, the sixth region and the seventh region have.

17. 发明申请

US20230085420A1 DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION 有权
公开(公告)号：US20230085420A1
公开(公告)日：2023-03-16
申请号：US17471190
申请日：2021-09-10
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Prantik MAHAJAN , Aloysius Priartanto HERLAMBANG , Kyong Jin HWANG , Robert John GAUTHIER, JR.
IPC分类号： H01L27/02 , H01L27/06 , H01L21/8224 , H01L21/762
摘要： A device includes a first region, a second region disposed on the first region, a third region and a fourth region abutting the third region disposed in the second region, a fifth region disposed in the third region and coupled to a collector disposed above, and a sixth region disposed in the fourth region and coupled to an emitter disposed above. A first isolation is disposed between the collector and the emitter. A seventh region is disposed in the fifth region and coupled to the collector is spaced apart from the first isolation. The first region, the third region, the fifth region, the collector and the emitter have a first conductivity type different from a second conductivity type that the second region, the fourth region, the sixth region and the seventh region have.

18. 发明授权

US09048280B2 Vertical polysilicon-germanium heterojunction bipolar transistor 有权
标题翻译：垂直多晶硅 - 锗异质结双极晶体管
公开(公告)号：US09048280B2
公开(公告)日：2015-06-02
申请号：US13923906
申请日：2013-06-21
申请人： International Business Machines Corporation
发明人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L21/8224 , H01L29/737 , H01L29/66 , H01L21/762 , H01L21/8249 , H01L29/06 , H01L29/08 , H01L29/165
CPC分类号： H01L29/737 , H01L21/76229 , H01L29/0649 , H01L29/0821 , H01L29/165 , H01L29/66242 , H01L29/7375
摘要： A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.
摘要翻译：垂直异质结双极晶体管（HBT）包括具有掺杂第一导电类型的掺杂多晶硅作为具有约1.12eV的能带隙的宽间隙发射极，并且具有掺杂第二导电类型的掺杂单晶Ge作为基极具有约0.66eV的能量带隙。采用具有第一导电类型掺杂的掺杂单晶Ge作为集电体。因为基极和集电极包括具有相同晶格常数的相同的半导体材料即Ge，所以在集电极和基极之间不存在晶格失配问题。此外，由于发射极是多晶的并且基极是单晶的，所以在基极和发射极之间不存在晶格失配问题。

19. 发明申请

US20050082632A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20050082632A1
公开(公告)日：2005-04-21
申请号：US10950611
申请日：2004-09-27
申请人： Ryo Kanda , Shigeaki Okawa , Kazuhiro Yoshitaka
发明人： Ryo Kanda , Shigeaki Okawa , Kazuhiro Yoshitaka
IPC分类号： H01L21/74 , H01L21/761 , H01L21/8222 , H01L21/8224 , H01L21/8226 , H01L21/8228 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L29/732 , H01L29/423
CPC分类号： H01L21/8224 , H01L27/0821 , H01L29/7322
摘要： A semiconductor integrated circuit device according to the present invention includes an N-type embedded diffusion region between a substrate and an epitaxial layer in first and second island regions serving as small signal section. The N-type embedded diffusion region connects to N-type diffusion regions having supply potential. The substrate and the epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.
摘要翻译：根据本发明的半导体集成电路器件包括用作小信号部分的第一和第二岛区中的衬底和外延层之间的N型嵌入扩散区域。 N型嵌入扩散区域连接到具有电源电位的N型扩散区域。因此，衬底和外延层被用作小信号部分的岛区域中具有电源电位的N型嵌入式扩散区域分隔开。这种结构防止由于电动机的反电动势进入小信号部分而从电力NPN晶体管产生的自由载流子（电子）的流入，从而防止小信号部分的故障。

20. 发明授权

US6150225A Method for fabricating a semiconductor device having vertical and lateral type bipolar transistors 失效
标题翻译：制造具有垂直和横向型双极晶体管的半导体器件的方法
公开(公告)号：US6150225A
公开(公告)日：2000-11-21
申请号：US991298
申请日：1997-12-16
申请人： Seiichi Takahashi
发明人： Seiichi Takahashi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8224 , H01L21/8228 , H01L27/082 , H01L29/732
CPC分类号： H01L21/8224 , H01L27/0821
摘要： A semiconductor device has a P type semiconductor substrate 1, a vertical type bipolar transistor having an N type base region 4, a lateral type bipolar transistor having an N type base region 4 formed on the semiconductor substrate 1, an N type collector region 7a, and an N type emitter region 8, and a P type insulating diffusion region 7b for isolating between vertical and lateral type bipolar transistors, at least one of collector and emitter regions of the lateral bipolar transistor having substantially same depth of the insulating diffusion region 7b.
摘要翻译：半导体器件具有P型半导体衬底1，具有N型基极区域4的垂直型双极晶体管，在半导体衬底1上形成有N型基极区域4的横向型双极晶体管，N型集电极区域7a， N型发射极区域8和用于在垂直和横向型双极晶体管之间隔离的P型绝缘扩散区域7b，所述横向双极晶体管的集电极和发射极区中的至少一个具有与绝缘扩散区域7b基本相同的深度。

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