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11. 发明授权

US06434587B1 Fast 16-B early termination implementation for 32-B multiply-accumulate unit 失效
标题翻译：快速16-B提前终止实现32-B乘法累加单元
公开(公告)号：US06434587B1
公开(公告)日：2002-08-13
申请号：US09333153
申请日：1999-06-14
申请人： Yuyun Liao , David Roberts
发明人： Yuyun Liao , David Roberts
IPC分类号： G06F752
CPC分类号： G06F7/5324 , G06F7/5318 , G06F7/5338 , G06F7/5443 , G06F2207/382
摘要： An embodiment of the present invention is a mixed length encoding unit. The mixed length may be a 12/16 bits (12/16-b) encoding algorithm within a multiply-accumulate (MAC). The mixed length encoding unit includes 16-b Booth encoder adapted to produce eight partial product vectors from sixteen bits of data. The 16-b Booth encoder is coupled to a four stage Wallace Tree. During a first cycle of the invention, a multiplex system directs the eight partial products and an accumulation vector to a four stage Wallace Tree. During subsequent cycles, the multiplex system directs six partial product vectors, an accumulation vector, one carry-feedback input vector, and one sum-feedback input vector to the four stage Wallace Tree.
摘要翻译：本发明的实施例是混合长度编码单元。混合长度可以是乘法累加（MAC）中的12/16位（12/16-b）编码算法。混合长度编码单元包括16-B布斯编码器，其适于从十六位数据产生八个部分乘积向量。 16-B布斯编码器连接到四级华莱士树。在本发明的第一周期期间，多路复用系统将八个部分产品和累积向量引导到四阶华莱士树。在后续周期中，多路复用系统将六个部分乘积向量，累加向量，一个进位反馈输入向量和一个和反馈输入向量引导到四阶华莱士树。

12. 发明授权

US06415311B1 Sign extension circuit and method for unsigned multiplication and accumulation 有权
标题翻译：符号扩展电路和无符号乘法和积累方法
公开(公告)号：US06415311B1
公开(公告)日：2002-07-02
申请号：US09344175
申请日：1999-06-24
申请人： Stephen C. Purcell , Nital P. Patwa
发明人： Stephen C. Purcell , Nital P. Patwa
IPC分类号： G06F752
CPC分类号： G06F7/5443
摘要： A carry save multiplier receives two input values having respective bit lengths A and B and provides sum and carry values, each having bit lengths A+B+1. A carry prediction circuit receives the most significant bit of the sum and carry values and provides an extension bit to be merged with less significant bits of the sum and carry bits. A carry save adder receives the altered sum and carry values, as well as a third input value to provide second sum and carry values. The second sum and carry values are added in a carry propagate adder to form a resulting value. This allows for a faster multiplication to form a product, and the faster addition of this product to another value such as an accumulator value.
摘要翻译：进位保存乘法器接收具有相应位长度A和B的两个输入值，并提供各自具有位长度A + B + 1的和值和进位值。进位预测电路接收和的最高有效位并携带值，并提供一个扩展位，并将其与较低有效位并入和传送位合并。进位保存加法器接收改变的和和进位值，以及第三输入值以提供第二和值和进位值。第二个和进位值被附加在进位传播加法器中以形成结果值。这允许更快的乘法来形成产品，并且将该产品更快地添加到另一个值，例如累加器值。

13. 发明授权

US06351760B1 Division unit in a processor using a piece-wise quadratic approximation technique 有权
标题翻译：使用分段二次逼近技术的处理器中的分割单元
公开(公告)号：US06351760B1
公开(公告)日：2002-02-26
申请号：US09240312
申请日：1999-01-29
申请人： Ravi Shankar , Subramania I. Sudharsanan
发明人： Ravi Shankar , Subramania I. Sudharsanan
IPC分类号： G06F752
CPC分类号： G06F7/535 , G06F7/4873 , G06F7/49947 , G06F7/49957 , G06F7/49963 , G06F9/30014 , G06F2207/3884
摘要： A computation unit computes a division operation Y/X by determining the value of a divisor reciprocal 1/X and multiplying the reciprocal by a numerator Y. The reciprocal 1/X value is determined using a quadratic approximation having a form: Ax2+Bx+C, where coefficients A, B, and C are constants that are stored in a storage or memory such as a read-only memory (ROM). The bit length of the coefficients determines the error in a final result. Storage size is reduced through use of “least mean square error”techniques in the determination of the coefficients that are stored in the coefficient storage. During the generation of partial products x2, Ax2, and Bx, the process of rounding is eliminated, thereby reducing the computational logic to implement the division functionality.
摘要翻译：计算单元通过确定除数互逆1 / X的值并将倒数乘以分子Y来计算除法运算Y / X。使用具有以下形式的二次近似来确定倒数1 / X值：其中系数A， B和C是存储在诸如只读存储器（ROM）的存储器或存储器中的常数。系数的位长决定了最终结果中的误差。在确定系数存储器中存储的系数时，通过使用“最小均方误差”技术来减少存储大小。在部分产品x2，Ax2和Bx的生成期间，舍入的过程被消除，从而减少了实现分割功能的计算逻辑。

14. 发明授权

US06311203B1 Multiplier, and fixed coefficient FIR digital filter having plural multipliers 失效
标题翻译：具有多个乘法器的乘法器和固定系数FIR数字滤波器
公开(公告)号：US06311203B1
公开(公告)日：2001-10-30
申请号：US09203373
申请日：1998-12-02
申请人： Yasushi Wada , Shuji Murakami
发明人： Yasushi Wada , Shuji Murakami
IPC分类号： G06F752
CPC分类号： H03H17/06 , G06F7/523
摘要： A multiplication device for performing a multiplication operation on a multiplicand X and two fixed coefficients C1 and C2 where C1>C2. The multiplication device comprises a multiplier for multiplying multiplicand X and the average CA of the two fixed coefficients C1 and C2; a shift register for obtaining a sum of the multiplicand X data after being shifted up according to a position of a “1” bit in bit data where the bit data is the remainder coefficient obtained by subtracting average CA from fixed coefficient C1; and a selector for selecting a product obtained for one of the fixed coefficients C1 and C2. When the fixed coefficient C1 is selected, the selector outputs the sum of the product returned by the multiplier and the accumulated value obtained by the shift register; when fixed coefficient C2 is selected, the selector outputs the difference of the product returned by the multiplier minus the accumulated value obtained by the shift register. A fixed coefficient FIR digital filter having a plurality of multiplication devices above-mentioned is also disclosed.
摘要翻译：用于对被乘数X和两个固定系数C1和C2执行乘法运算的乘法装置，其中C1> C2。乘法装置包括用于将被乘数X与两个固定系数C1和C2的平均CA相乘的乘法器; 移位寄存器，用于根据比特数据中的“1”位的位置向上移位被乘数X数据，其中比特数据是通过从固定系数C1减去平均CA而获得的余数系数; 以及选择器，用于选择为固定系数C1和C2之一获得的乘积。当选择固定系数C1时，选择器输出由乘法器返回的乘积和由移位寄存器获得的累加值之和; 当选择固定系数C2时，选择器输出由乘数返回的乘积的差值减去由移位寄存器获得的累加值。还公开了具有上述多个乘法装置的固定系数FIR数字滤波器。

15. 发明授权

US06275842B1 Low power multiplier for CPU and DSP 有权
标题翻译： CPU和DSP的低功率乘法器
公开(公告)号：US06275842B1
公开(公告)日：2001-08-14
申请号：US09431851
申请日：1999-11-02
申请人： Christopher John Nicol
发明人： Christopher John Nicol
IPC分类号： G06F752
CPC分类号： G06F7/5338 , H03K19/215
摘要： The NEG output of the Booth encoding circuit and the multiplicand input are gated so as to minimize switching activity in the multiplier without adding any delay to the critical path thereof. Advantageously, power consumption in the multiplier is significantly reduced, e.g., on the order of 90%, when multiplication is in fact not being performed. Additionally, by changing the structure of the last XOR gate of the partial product generation circuit, the need to gate the multiplicand input can be eliminated. Advantageously, this eliminates the extra circuitry which would otherwise be required to gate the multiplicand input, thus reducing cost. Furthermore, additional power savings may be achieved by efficiently resynchronizing the multiplicand input with the Booth encoded input to the partial product circuit.
摘要翻译：展位编码电路和被乘数输入的NEG输出被选通，以便最小化乘法器中的开关活动，而不对其关键路径增加任何延迟。有利地，当实际上不执行乘法时，乘法器中的功率消耗被显着地减小，例如大约90％。此外，通过改变部分乘积产生电路的最后的异或门的结构，可以消除对被乘数输入进行门控的需要。有利地，这消除了额外的电路，否则将需要门电路被乘数输入，从而降低成本。此外，通过将乘法器输入与布尔编码的输入有效地重新同步到部分乘积电路，可以实现额外的功率节省。

16. 发明授权

US06202077B1 SIMD data processing extended precision arithmetic operand format 失效
标题翻译： SIMD数据处理扩展精度算术运算格式
公开(公告)号：US06202077B1
公开(公告)日：2001-03-13
申请号：US09028846
申请日：1998-02-24
申请人： Roger Alan Smith
发明人： Roger Alan Smith
IPC分类号： G06F752
CPC分类号： G06F7/5443 , G06F7/723 , G06F7/728 , G06F9/30014 , G06F2207/3828
摘要： Two related extended precision operand formats provide for efficient multiply/accumulate operations in a SIMD data processing system. Each format utilizes a group of “b” bit elements in a vector register. Each of the elements provides “m” bits of precision, with b>m. The remaining b−m bits in each element accumulate overflows and carries across multiple additions and subtractions. Existing SIMD multiply-sum instructions can be used to efficiently take input operands from the first format and produce output results in the second extended precision format when b2=2b1 and m2=2m1.
摘要翻译：两个相关的扩展精度操作数格式在SIMD数据处理系统中提供有效的乘法/累加操作。每个格式在向量寄存器中使用一组“b”位元素。每个元素提供“m”位精度，b> m。每个元素中的剩余b-m位会累积溢出并进行多次加法和减法。可以使用现有的SIMD乘法和指令来有效地从第一格式获取输入操作数，并且当b2 = 2b1和m2 = 2m1时，产生第二扩展精度格式的输出结果。

17. 发明授权

US06816877B2 Apparatus for digital multiplication using redundant binary arithmetic 失效
标题翻译：使用冗余二进制算术进行数字乘法的装置
公开(公告)号：US06816877B2
公开(公告)日：2004-11-09
申请号：US09832869
申请日：2001-04-12
申请人： Hong-june Park , Sang-hoon Lee
发明人： Hong-june Park , Sang-hoon Lee
IPC分类号： G06F752
CPC分类号： G06F7/5336 , G06F7/4824
摘要： A digital multiplication apparatus and method adopting redundant binary arithmetic is provided. In this digital multiplication apparatus, when two numbers X and Y are multiplied using a radix-2k number system, a data converter data-converts the m-bit number Y into m/k digit data D (=Dm/k−1Dm/k−2 . . . Di . . . DiDo). A partial product calculator converts each of the digits Di of the number Y converted by the data converter into a combination of the coefficients of a fundamental multiple, multiplies the combination by the number X, and outputs the product as a redundant binary partial product. A redundant binary adder sums the partial products for all of the digits of the converted number Y. A redundant binary (RB)-normal binary (NB) converter converts the redundant binary sum into a normal binary number and outputs the converted normal binary sum as the product of the two numbers. Therefore, even when the radix extends, the burden upon hardware can be minimized. Also, many systems having multipliers serving as important components can be more simply constructed.
摘要翻译：提供了采用冗余二进制算术的数字乘法装置和方法。在该数字乘法装置中，当使用基数-2k数字系统对两个数X和Y进行相乘时，数据转换器将m位数Y转换成m / k位数据D（= Dm / k-1Dm / k -2。。Di。。DiDo）。部分乘积计算器将由数据转换器转换的数字Y的数字Di中的每一个转换为基本倍数的系数的组合，将组合乘以数X，并将该乘积作为冗余二进制部分乘积输出。冗余二进制加法器将所转换的数字Y的所有数字的部分乘积相加。冗余二进制（RB） - 正常二进制（NB）转换器将冗余二进制和转换为正常二进制数，并将转换后的正态二进制和作为这两个数字的产物。因此，即使基数延长，硬件上的负担也可以最小化。此外，可以更简单地构造具有用作重要部件的乘法器的许多系统。

18. 发明授权

US06785702B2 Energy saving multiplication device and method 有权
标题翻译：节能倍增装置及方法
公开(公告)号：US06785702B2
公开(公告)日：2004-08-31
申请号：US09861572
申请日：2001-05-22
申请人： Oscal T.-C. Chen , Kuo-Hua Chen , Ruey-Liang Ma
发明人： Oscal T.-C. Chen , Kuo-Hua Chen , Ruey-Liang Ma
IPC分类号： G06F752
CPC分类号： G06F7/49942 , G06F7/52
摘要： An energy saving multiplication device and its method is disclosed. The multiplication device includes a dynamic range determination unit, a Booth encoding/decoding unit and a counter array. The dynamic range determination unit determines dynamic ranges of the numerical values to be multiplied together and outputs after processing according to the dynamic-range size relation of the input data. The Booth encoding/decoding unit couples to the dynamic range determination unit. The counter array couples to the Booth encoding/decoding unit for accumulating the partial products to obtain the products of the input data.
摘要翻译：公开了一种节能倍增装置及其方法。乘法装置包括动态范围确定单元，布尔编码/解码单元和计数器阵列。动态范围确定单元确定要相乘的数值的动态范围，并根据输入数据的动态范围大小关系在处理之后输出。展位编码/解码单元耦合到动态范围确定单元。计数器阵列耦合到布斯编码/解码单元，用于累积部分乘积以获得输入数据的乘积。

19. 发明授权

US06772186B1 Multimedia multiply-adder 有权
标题翻译：多媒体加法器
公开(公告)号：US06772186B1
公开(公告)日：2004-08-03
申请号：US09618560
申请日：2000-07-18
申请人： Motonobu Tonomura , Fumio Arakawa
发明人： Motonobu Tonomura , Fumio Arakawa
IPC分类号： G06F752
CPC分类号： G06F7/5443 , G06F7/4991 , G06F7/49994 , G06F7/5318 , G06F2207/3828
摘要： A multimedia processor is capable of concurrently carrying out processing tasks at different degrees of precision suitable for a variety of purposes and displays high performance of consecutively outputting a new cumulative result by adding or subtracting a result of multiplication to or from an existing cumulative result. To prevent the processing precision from deteriorating in applications where the processing precision is critical, critical processing precision is assured by multiplication of a signed number by an unsigned number. A partial product output by a multiplication and an existing cumulative result are supplied. The number of inputs is counted by a carry-save counter based on a 7-3 counter. A ripple adder is employed on the low-order-digit side where propagation of carry is completed early. On the other hand, a carry select/look-ahead adder is employed on the high-order-digit side to speed up the propagation of a carry. In this way, a multimedia multiply adder/subtractor can be assembled with a small number of gate stages. As a result, there is exhibited an effect that, when it is desired to store a series of multiplication results obtained consecutively, a carry-save result produced in a middle of one machine cycle can be input and stored for further use when an eventual result of propagation of a carry can not be output during the one machine cycle.
摘要翻译：多媒体处理器能够以适合各种目的的不同精度的同时执行处理任务，并且通过将现有累积结果的乘法结果相加或相减来连续地输出新的累积结果的高性能。为了防止处理精度在处理精度至关重要的应用中处理精度降低，通过将有符号数乘以无符号数来确保关键处理精度。提供乘法和现有累积结果的部分乘积输出。基于7-3计数器的进位保存计数器对输入数进行计数。在进位传播早期完成的低位数字侧采用纹波加法器。另一方面，在高位数侧采用进位选择/预读加法器，以加速进位的传播。以这种方式，多路复用加法器/减法器可以用少量门级组合。结果，显示了当希望存储连续获得的一系列相乘结果时，可以输入并存储在一个机器周期的中间产生的进位保存结果，以便在最终结果时进一步使用在一个机器周期期间不能输出进位的传播。

20. 发明授权

US06742011B1 Apparatus and method for increasing performance of multipliers utilizing regular summation circuitry 有权
标题翻译：利用常规求和电路提高乘法器性能的装置和方法
公开(公告)号：US06742011B1
公开(公告)日：2004-05-25
申请号：US09504984
申请日：2000-02-15
申请人： Glenn T Colon-Bonet , Stephen L Bass , Thomas J. Sullivan
发明人： Glenn T Colon-Bonet , Stephen L Bass , Thomas J. Sullivan
IPC分类号： G06F752
CPC分类号： G06F7/5336
摘要： The present invention generally relates to an apparatus and method for efficiently summing the partial product bits produced by a multiplier. Briefly described, in architecture, the apparatus includes a first array of odd/even summation circuitry, a second array of odd/even summation circuitry, and a linear array of adders. The apparatus is configured to add a row of partial product bits produced by a multiplier in multiplying a first operand with a second operand. The first array of odd/even summation circuitry produces a first summation of a portion of the partial product bits. The second array of odd/even circuitry produces a second summation of the other partial product bits. The linear array of adders then adds the first summation and the second summation to produce a carry save representation of a product bit (i.e., a bit of the product produced by multiplying the first operand by the second operand).
摘要翻译：本发明一般涉及一种用于有效地求和由乘法器产生的部分乘积位的装置和方法。简要描述，在架构中，该装置包括奇/偶求和电路的第一阵列，奇/偶求和电路的第二阵列和加法器的线性阵列。该装置被配置为在第一操作数与第二操作数相乘中添加由乘法器产生的一部分乘积位。奇/偶求和电路的第一阵列产生部分乘积比特的一部分的第一和。奇数/偶数电路的第二阵列产生其他部分乘积位的第二和。然后，加法器的线性阵列将第一和和第二求和相加以产生乘积比特的进位保存表示（即，通过将第一操作数乘以第二操作数而产生的乘积的位）。

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