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1. 发明授权

US06785702B2 Energy saving multiplication device and method 有权
标题翻译：节能倍增装置及方法
公开(公告)号：US06785702B2
公开(公告)日：2004-08-31
申请号：US09861572
申请日：2001-05-22
申请人： Oscal T.-C. Chen , Kuo-Hua Chen , Ruey-Liang Ma
发明人： Oscal T.-C. Chen , Kuo-Hua Chen , Ruey-Liang Ma
IPC分类号： G06F752
CPC分类号： G06F7/49942 , G06F7/52
摘要： An energy saving multiplication device and its method is disclosed. The multiplication device includes a dynamic range determination unit, a Booth encoding/decoding unit and a counter array. The dynamic range determination unit determines dynamic ranges of the numerical values to be multiplied together and outputs after processing according to the dynamic-range size relation of the input data. The Booth encoding/decoding unit couples to the dynamic range determination unit. The counter array couples to the Booth encoding/decoding unit for accumulating the partial products to obtain the products of the input data.
摘要翻译：公开了一种节能倍增装置及其方法。乘法装置包括动态范围确定单元，布尔编码/解码单元和计数器阵列。动态范围确定单元确定要相乘的数值的动态范围，并根据输入数据的动态范围大小关系在处理之后输出。展位编码/解码单元耦合到动态范围确定单元。计数器阵列耦合到布斯编码/解码单元，用于累积部分乘积以获得输入数据的乘积。

2. 发明授权

US06629119B1 Arithmetic device and method with low power consumption 有权
标题翻译：具有低功耗的算术装置和方法
公开(公告)号：US06629119B1
公开(公告)日：2003-09-30
申请号：US09452219
申请日：1999-12-01
申请人： Oscal T. -C. Chen , I-Ping Hsu , Ruey-Liang Ma
发明人： Oscal T. -C. Chen , I-Ping Hsu , Ruey-Liang Ma
IPC分类号： G06F752
CPC分类号： G06F7/57 , G06F2207/3816
摘要： An arithmetic device with low power consumption includes master latches, a dynamic range detection unit, slave latches, an operation unit, and a word-length restoration unit. In the arithmetic device, the master latches latch a plurality of (such as two) input data. The dynamic range detection unit detects the effective dynamic range of these input data. The slave latches latch the values of the effective dynamic-range bits of these input data. The operation unit performs predetermined operations of the bits of these effective dynamic range to obtaing an operation result. Since the operation unit only performs operations of the bits of the effective dynamic range, the circuit corresponding to other bits will not demonstrate switching of power consumption, thereby lowering the overall power consumption. Furthermore, the word-length restoration unit will complement the operation result to its original output length in association with the sign of the operation result, for obtaining the correct operation result.
摘要翻译：具有低功耗的算术装置包括主锁存器，动态范围检测单元，从锁存器，操作单元和字长恢复单元。在算术装置中，主锁存器锁存多个（如两个）输入数据。动态范围检测单元检测这些输入数据的有效动态范围。从锁存器锁存这些输入数据的有效动态范围位的值。操作单元执行这些有效动态范围的位的预定操作以获得操作结果。由于操作单元仅执行有效动态范围的位的操作，所以对应于其他位的电路将不会显示功耗的切换，从而降低总功耗。此外，字长恢复单元将与操作结果的符号相关联的操作结果与其原始输出长度相匹配，以获得正确的操作结果。

3. 发明申请

US20050021578A1 Reconfigurable apparatus with a high usage rate in hardware 审中-公开
标题翻译：硬件使用率高的可重构设备
公开(公告)号：US20050021578A1
公开(公告)日：2005-01-27
申请号：US10730114
申请日：2003-12-09
申请人： Li-Hsun Chen , Oscal T. -C. Chen , Teng Wang , Ruey-Liang Ma
发明人： Li-Hsun Chen , Oscal T. -C. Chen , Teng Wang , Ruey-Liang Ma
IPC分类号： G06F7/38 , G06F7/57 , G06F15/78
CPC分类号： G06F9/30014 , G06F7/57 , G06F9/3885 , G06F9/3897 , G06F15/7867
摘要： A reconfigurable apparatus with a high usage rate in hardware is disclosed, which comprises at least one reconfigurable unit that has a plurality of processing units and at least one switch box connected to the processing units. The reconfigurable unit receives at least one reconfiguration signal to dynamically configure the processing units and the switch boxes as a new functional unit.
摘要翻译：公开了一种在硬件中具有高使用率的可重构设备，其包括具有多个处理单元和至少一个与处理单元连接的开关盒的至少一个可重新配置单元。可重配置单元接收至少一个重新配置信号，以将处理单元和交换机框动态配置为新的功能单元。

4. 发明授权

US07073049B2 Non-copy shared stack and register file device and dual language processor structure using the same 失效
公开(公告)号：US07073049B2
公开(公告)日：2006-07-04
申请号：US10223295
申请日：2002-08-20
申请人： Ruey-Liang Ma , Shih-Wei Peng
发明人： Ruey-Liang Ma , Shih-Wei Peng
IPC分类号： G06F9/30
CPC分类号： G06F9/30134 , G06F9/30174
摘要： The present invention provides a non-copy shared stack and register set device and a dual language processor structure using the same, which achieve non-copy data sharing by controlling a selector and the stack pointer of a data stack. The selector is connected to each item of the data stack and a register of the register set, such that, when the register set requires to exchange data with the data stack, the selector is controlled and the stack pointer is updated thereby the selector is switched to make the stack item pointed by the stack pointer communicate with the register.

5. 发明授权

US5948100A Branch prediction and fetch mechanism for variable length instruction, superscalar pipelined processor 失效
标题翻译：可变长度指令，超标量流水线处理器的分支预测和获取机制
公开(公告)号：US5948100A
公开(公告)日：1999-09-07
申请号：US972226
申请日：1997-11-17
申请人： Chia-Chang Hsu , Ruey-Liang Ma , Chien-Kuo Tien , Kun-Cheng Wu
发明人： Chia-Chang Hsu , Ruey-Liang Ma , Chien-Kuo Tien , Kun-Cheng Wu
IPC分类号： G06F9/30 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3806 , G06F9/30149 , G06F9/3804 , G06F9/3816 , G06F9/3844
摘要： A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed. The fetcher also generates a search address for output to the branch target buffer. In response to the branch target buffer detecting a taken branch that crosses multiple cache blocks, the fetch address is increased so that it points to the next cache block to be fetched but the search address is maintained the same.
摘要翻译：公开了一种处理器架构，包括一个提取器，分组单元和分支目标缓冲器。分支目标缓冲器设置有以组合关联方式组织的标签RAM。响应于接收到搜索地址，标签RAM中的多个集合被同时搜索预测要被采用的分支指令。分组单元具有包含指令的被存储的高速缓存块所存储的队列。顺序获取的高速缓存块存储在队列的相邻位置。队列条目还具有指示指示序列的起始或最终数据字是否包含在队列条目中的指示符，如果是，则指示特定起始数据字或最终数据字的偏移量。作为响应，分组单元将指令序列的数据字连接成连续的块。提取器产生一个取出地址，用于从包含要执行的指令的指令高速缓存中提取缓存块。读取器还生成用于输出到分支目标缓冲区的搜索地址。响应于分支目标缓冲器检测跨越多个高速缓存块的取得的分支，提取地址增加，使得它指向要获取的下一个高速缓存块，但是搜索地址保持相同。

6. 发明授权

US06382846B1 Intermediate instruction execution processor which resolves symbolic references without modifying intermediate instruction code 失效
标题翻译：中间指令执行处理器，可在不修改中间指令代码的情况下解析符号引用
公开(公告)号：US06382846B1
公开(公告)日：2002-05-07
申请号：US09004870
申请日：1998-01-09
申请人： George Shiang-Jyh Lai , Ruey-Liang Ma , Dze-chaung Wang , Shi-Sheng Shang , Kun-Cheng Wu
发明人： George Shiang-Jyh Lai , Ruey-Liang Ma , Dze-chaung Wang , Shi-Sheng Shang , Kun-Cheng Wu
IPC分类号： G06F945
CPC分类号： G06F9/44521
摘要： A processor is provided with a decoder, a memory connected to the decoder and an execution stage connected to the decoder. The decoder receives each instruction. Each time the decoder receives an instruction, if the instruction contains a symbolic reference, the decoder determines whether or not the symbolic reference has been resolved into a numeric operand. If the symbolic reference has been resolved into a numeric operand, the memory retrieves, from a numeric reference table, a numeric operand to which the symbolic reference has been resolved. The execution stage then executes the instruction on the retrieved numeric operand in place of the symbolic reference. If the symbolic reference has not been resolved into a numeric operand, then the execution stage searches a data object, which relates each symbolic reference to a memory slot in which a corresponding numeric operand is stored, for a numeric reference relating the symbolic reference to a corresponding numeric operand. The memory then retrieves the numeric operand, that corresponds to the unresolved symbolic reference, from the memory slot indicated by the numeric reference of the data object. The memory stores the retrieved numeric operand in the numeric reference table maintained therein. The execution stage executes the instruction on the retrieved numeric operand in place of the symbolic reference of the instruction and indicates to the decoder that the symbolic reference is resolved. “Resolved indications,” which each indicates whether or not a specific, respective symbolic reference is resolved, can be stored in a numeric reference buffer and accessed using the instruction fetch address as an index. The numeric reference table can also be stored in the numeric reference buffer and accessed (indexed) the same way.
摘要翻译：处理器设置有解码器，连接到解码器的存储器和连接到解码器的执行级。解码器接收每条指令。每当解码器接收到指令时，如果指令包含符号参考，则解码器确定符号引用是否已被解析为数字操作数。如果符号引用已被解析为数字操作数，则内存将从数字参考表中检索已解析符号引用的数字操作数。执行阶段然后执行关于检索的数字操作数的指令代替符号引用。如果符号引用尚未解析成数字操作数，则执行阶段搜索数据对象，该数据对象将每个符号引用与其中存储对应的数字操作数的存储器槽相关联，用于将符号引用与数字对象相关联对应的数字操作数。然后，存储器从数据对象的数字参考指示的存储槽中检索对应于未解析的符号引用的数字操作数。存储器将检索的数字操作数存储在其中维护的数字参考表中。执行级代替检索的数字操作数的指令代替指令的符号引用，并向解码器指示符号引用被解析。 “解决的指示”，其各自指示特定的相应符号引用是否被解析，可以存储在数字参考缓冲器中并且使用指令获取地址作为索引进行访问。数字参考表也可以存储在数字参考缓冲区中，以相同的方式访问（索引）。

7. 发明授权

US6035387A System for packing variable length instructions into fixed length blocks with indications of instruction beginning, ending, and offset within block 有权
标题翻译：将可变长度指令打包成固定长度块的系统，具有指令开始，结束和偏移量的指示
公开(公告)号：US6035387A
公开(公告)日：2000-03-07
申请号：US324236
申请日：1999-06-02
申请人： Chia-Chang Hsu , Ruey-Liang Ma , Chien-kuo Tien , Kun-Cheng Wu
发明人： Chia-Chang Hsu , Ruey-Liang Ma , Chien-kuo Tien , Kun-Cheng Wu
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/30149 , G06F9/3804 , G06F9/3816 , G06F9/3844
摘要： A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed. The fetcher also generates a search address for output to the branch target buffer. In response to the branch target buffer detecting a taken branch that crosses multiple cache blocks, the fetch address is increased so that it points to the next cache block to be fetched but the search address is maintained the same.
摘要翻译：公开了一种处理器架构，包括一个提取器，分组单元和分支目标缓冲器。分支目标缓冲器设置有以组合关联方式组织的标签RAM。响应于接收到搜索地址，标签RAM中的多个集合被同时搜索预测要被采用的分支指令。分组单元具有存储包含指令的获取的高速缓存块的队列。顺序获取的高速缓存块存储在队列的相邻位置。队列条目还具有指示指示序列的起始或最终数据字是否包含在队列条目中的指示符，如果是，则指示特定起始数据字或最终数据字的偏移量。作为响应，分组单元将指令序列的数据字连接成连续的块。提取器产生一个取出地址，用于从包含要执行的指令的指令高速缓存中提取缓存块。读取器还生成用于输出到分支目标缓冲区的搜索地址。响应于分支目标缓冲器检测跨越多个高速缓存块的被采取的分支，提取地址增加，使得它指向要获取的下一个高速缓存块，但是搜索地址保持相同。

8. 发明授权

US6006323A Intelligent multiple stack management unit 失效
标题翻译：智能多堆栈管理单元
公开(公告)号：US6006323A
公开(公告)日：1999-12-21
申请号：US82368
申请日：1998-05-20
申请人： Ruey-Liang Ma , Shi-Sheng Shang
发明人： Ruey-Liang Ma , Shi-Sheng Shang
IPC分类号： G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/30101 , G06F9/30134 , G06F9/4425
摘要： A stack management unit for a processing system that manages multiple stacks and corresponding stack pointer data as a frame stack. The stack management unit utilizes a combination of a primary stack and a secondary stack as the frame stack. A background spill/fill detect unit determines when an overflow/underflow of the primary stack occurs. In response to an overflow/underflow condition, the background spill/fill detect unit controls the transfer of a frame portion between the primary stack and the secondary stack without halting the processing system.
摘要翻译：用于处理系统的堆栈管理单元，其将多个堆栈和相应的堆栈指针数据管理为帧堆栈。堆栈管理单元利用主栈和二栈的组合作为帧栈。背景溢出/填充检测单元确定何时发生主栈的溢出/下溢。响应于溢出/下溢条件，背景溢出/填充检测单元控制主堆栈和辅助堆栈之间的帧部分的传送而不停止处理系统。

9. 发明授权

US5974531A Methods and systems of stack renaming for superscalar stack-based data processors 失效
标题翻译：基于超标量堆栈的数据处理器的堆栈重命名方法和系统
公开(公告)号：US5974531A
公开(公告)日：1999-10-26
申请号：US24752
申请日：1998-02-17
申请人： Shi-Sheng Shang , Ruey-Liang Ma , Dze-Chaung Wang
发明人： Shi-Sheng Shang , Ruey-Liang Ma , Dze-Chaung Wang
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F12/02
CPC分类号： G06F9/3017 , G06F9/3004 , G06F9/30101 , G06F9/30163 , G06F9/30167 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： Methods and systems are disclosed for exploring instruction-level parallelism in superscalar processors by renaming stack entries. In a first embodiment, the stack renaming is implemented in a parallel structure that renames the instructions in parallel. In a second embodiment, the stack renaming is implemented in a serial structure that renames the instructions serially. In a third embodiment, the stack renaming is implemented in a combined parallel-serial structure that renames the instruction partially in parallel and partially in series.
摘要翻译：公开了通过重新命名堆栈条目来探索超标量处理器中的指令级并行性的方法和系统。在第一实施例中，堆栈重命名以并行结构实现，并行地重命名指令。在第二实施例中，堆栈重命名以串行结构实现，该串行结构重新命名指令。在第三实施例中，堆栈重命名以组合的并行串行结构实现，其将部分并行并部分地串联的指令重命名。

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