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    • 11. 发明授权
    • Method and apparatus for accurate clock synthesis
    • 用于精确时钟合成的方法和装置
    • US08248113B2
    • 2012-08-21
    • US12861067
    • 2010-08-23
    • Hong-Yean HsiehChia-Liang (Leon) Lin
    • Hong-Yean HsiehChia-Liang (Leon) Lin
    • H03B21/00
    • H03K3/011H03L1/026H03L1/027H03L7/099H03L7/1974
    • Methods and apparatus are provided in the present invention to adjust the frequency of an output clock close to within a required accuracy of an oscillation frequency. In another embodiment, a method comprises: entering a calibration mode; generating a first control word to control a timing of a clock synthesizer; adjusting the first control word until the timing of the clock synthesizer is sufficiently accurate with respect to a timing of a reference clock; sensing a temperature using a temperature sensor; storing a present value of an output of the temperature sensor and the first control word into a non-volatile memory; exiting the calibration mode; entering a normal operation mode; sensing the temperature using the temperature sensor; generating a second control word to control the timing of the clock synthesizer in accordance with an output of the non-volatile memory and the output of the temperature sensor.
    • 在本发明中提供了方法和装置,以将输出时钟的频率调整到振荡频率所要求的精度之内。 在另一个实施例中,一种方法包括:输入校准模式; 生成第一控制字以控制时钟合成器的定时; 调整第一控制字,直到时钟合成器的定时相对于参考时钟的定时足够精确; 使用温度传感器感测温度; 将温度传感器和第一控制字的输出的当前值存储到非易失性存储器中; 退出校准模式; 进入正常运行模式; 使用温度传感器感测温度; 产生第二控制字以根据非易失性存储器的输出和温度传感器的输出来控制时钟合成器的定时。
    • 13. 发明申请
    • CONFIGURABLE BASEBAND IN A GPS RECEIVER
    • GPS接收机中的可配置基带
    • US20120114018A1
    • 2012-05-10
    • US13352262
    • 2012-01-17
    • Richard Obermeyer
    • Richard Obermeyer
    • H04B1/7073
    • G01S19/37G01S19/235H03L1/027H03L1/028
    • Clock compensation for GPS receivers. A receiver in accordance with the present invention comprises a Radio Frequency (RF) portion, and a baseband portion, coupled to the RF portion, wherein the baseband portion comprises a crystal, an oscillator, coupled to the crystal, wherein the oscillator generates a clock signal based on a signal received from the crystal, a counter, coupled to the oscillator via the clock signal, a comparator, coupled to the counter, a controller, at least one logic gate, coupled to the comparator and the controller, and a combiner, coupled to the at least one logic gate, the controller, and the counter and producing an accurate clock signal therefrom.
    • GPS接收机的时钟补偿。 根据本发明的接收机包括耦合到RF部分的射频(RF)部分和基带部分,其中基带部分包括耦合到晶体的晶体,振荡器,其中振荡器产生时钟 基于从晶体接收的信号的信号,经由时钟信号耦合到振荡器的计数器,耦合到计数器的比较器,耦合到比较器和控制器的控制器,至少一个逻辑门,以及组合器 耦合到所述至少一个逻辑门,所述控制器和所述计数器并从其产生准确的时钟信号。
    • 17. 发明授权
    • Reference signal generation for multiple communication systems
    • 多通信系统的参考信号产生
    • US07742785B2
    • 2010-06-22
    • US11502232
    • 2006-08-09
    • Brian K. Harms
    • Brian K. Harms
    • H04M1/00
    • H03J7/065H03J2200/02H03L1/026H03L1/027H03L7/1976
    • Techniques for generating reference signals for multiple communication systems are described. An apparatus comprises a reference oscillator, a frequency control unit, and a plurality of frequency synthesizers. The reference oscillator generates a main reference signal and may be a crystal oscillator or some other type of oscillator. The frequency control unit estimates the frequency error of the main reference signal and provides a frequency error estimate. The plurality of frequency synthesizers receive the main reference signal and generate a plurality of system reference signals for a plurality of systems. At least one (e.g., each) frequency synthesizer corrects the frequency error of the main reference signal based on the frequency error estimate from the frequency control unit. Each frequency synthesizer may include a sigma-delta modulator used to generate a divider control for a phase locked loop (PLL). The divider control corrects for the frequency error of the main reference signal.
    • 描述用于产生多个通信系统的参考信号的技术。 一种装置包括参考振荡器,频率控制单元和多个频率合成器。 参考振荡器产生主参考信号,并且可以是晶体振荡器或其他类型的振荡器。 频率控制单元估计主参考信号的频率误差并提供频率误差估计。 多个频率合成器接收主参考信号并为多个系统生成多个系统参考信号。 至少一个(例如,每个)频率合成器基于来自频率控制单元的频率误差估计来校正主参考信号的频率误差。 每个频率合成器可以包括用于产生锁相环(PLL)的分频器控制的Σ-Δ调制器。 分频器控制校正主参考信号的频率误差。
    • 18. 发明授权
    • Frequency and/or phase compensated microelectromechanical oscillator
    • 频率和/或相位补偿微机电振荡器
    • US07532081B2
    • 2009-05-12
    • US11982084
    • 2007-10-31
    • Aaron PartridgeMarkus Lutz
    • Aaron PartridgeMarkus Lutz
    • H03B5/04H03B5/30H03L7/06
    • H03L1/022H03B5/04H03B5/30H03L1/026H03L1/027H03L1/04H03L7/07H03L7/08H03L7/0812H03L7/1974
    • There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a compensated microelectromechanical oscillator, having a microelectromechanical resonator that generates an output signal and frequency adjustment circuitry, coupled to the microelectromechanical resonator to receive the output signal of the microelectromechanical resonator and, in response to a set of values, to generate an output signal having second frequency. In one embodiment, the values may be determined using the frequency of the output signal of the microelectromechanical resonator, which depends on the operating temperature of the microelectromechanical resonator and/or manufacturing variations of the microelectromechanical resonator. In one embodiment, the frequency adjustment circuitry may include frequency multiplier circuitry, for example, PLLs, DLLs, digital/frequency synthesizers and/or FLLs, as well as any combinations and permutations thereof. The frequency adjustment circuitry, in addition or in lieu thereof, may include frequency divider circuitry, for example, DLLs, digital/frequency synthesizers (for example, DDS) and/or FLLs, as well as any combinations and permutations thereof.
    • 这里描述和说明了许多发明。 在一个方面,本发明涉及一种补偿的微机电振荡器,其具有产生输出信号和频率调节电路的微机电谐振器,耦合到微机电谐振器以接收微机电谐振器的输出信号,并响应于一组 以产生具有第二频率的输出信号。 在一个实施例中,可以使用取决于微机电谐振器的操作温度和/或微机电谐振器的制造变化的微机电谐振器的输出信号的频率来确定值。 在一个实施例中,频率调整电路可以包括倍频器电路,例如PLL,DLL,数字/频率合成器和/或FLL,以及它们的任何组合和排列。 频率调节电路,除了或代替它,可以包括分频器电路,例如DLL,数字/频率合成器(例如,DDS)和/或FLL,以及它们的任何组合和排列。
    • 20. 发明申请
    • Reference signal generation for multiple communication systems
    • 多通信系统的参考信号产生
    • US20080085693A1
    • 2008-04-10
    • US11502232
    • 2006-08-09
    • Brian K. Harms
    • Brian K. Harms
    • H04B1/06H04B7/00
    • H03J7/065H03J2200/02H03L1/026H03L1/027H03L7/1976
    • Techniques for generating reference signals for multiple communication systems are described. An apparatus comprises a reference oscillator, a frequency control unit, and a plurality of frequency synthesizers. The reference oscillator generates a main reference signal and may be a crystal oscillator or some other type of oscillator. The frequency control unit estimates the frequency error of the main reference signal and provides a frequency error estimate. The plurality of frequency synthesizers receive the main reference signal and generate a plurality of system reference signals for a plurality of systems. At least one (e.g., each) frequency synthesizer corrects the frequency error of the main reference signal based on the frequency error estimate from the frequency control unit. Each frequency synthesizer may include a sigma-delta modulator used to generate a divider control for a phase locked loop (PLL). The divider control corrects for the frequency error of the main reference signal.
    • 描述用于产生多个通信系统的参考信号的技术。 一种装置包括参考振荡器,频率控制单元和多个频率合成器。 参考振荡器产生主参考信号,并且可以是晶体振荡器或其他类型的振荡器。 频率控制单元估计主参考信号的频率误差并提供频率误差估计。 多个频率合成器接收主参考信号并为多个系统生成多个系统参考信号。 至少一个(例如,每个)频率合成器基于来自频率控制单元的频率误差估计来校正主参考信号的频率误差。 每个频率合成器可以包括用于产生锁相环(PLL)的分频器控制的Σ-Δ调制器。 分频器控制校正主参考信号的频率误差。