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11. 发明授权

US09448926B2 Bidirectional counter in a flash memory 有权
标题翻译：闪存中的双向计数器
公开(公告)号：US09448926B2
公开(公告)日：2016-09-20
申请号：US14634386
申请日：2015-02-27
申请人： Proton World International N.V.
发明人： Ronny Van Keer , Guillaume Docquier
IPC分类号： G06F12/00 , G06F13/00 , G06F12/02 , G06F9/30 , G11C16/10 , H03K21/40 , H03K23/56
CPC分类号： G06F12/0246 , G06F9/3001 , G06F2212/7207 , G11C16/105 , H03K21/403 , H03K23/56
摘要： A method of storing a counter in at least two non-volatile memory pages, including: a step of initializing a page with an initial value and then, on each update of the counter value, a step of storing an update value and an opcode associated with this value, selected from a set of opcodes, the current value of the counter being given by application of the successive update operations to the initial value of the page.
摘要翻译：一种在至少两个非易失性存储器页面中存储计数器的方法，包括：初始化具有初始值的页面的步骤，然后在计数器值的每次更新上存储更新值和操作码相关联的步骤通过从一组操作码中选择该值，通过将连续的更新操作应用于页面的初始值来给出计数器的当前值。

12. 发明申请

US20090195682A1 Counter array and image sensor including the same 有权
标题翻译：计数器阵列和图像传感器包括相同的
公开(公告)号：US20090195682A1
公开(公告)日：2009-08-06
申请号：US12320624
申请日：2009-01-30
申请人： Kyoung Min Koh , Kyung-Min Kim , Yong Lim
发明人： Kyoung Min Koh , Kyung-Min Kim , Yong Lim
IPC分类号： H04N5/335 , H03K21/08 , H03K21/16
CPC分类号： H03K23/56 , H04N5/378
摘要： A counter array and an image sensor including the same may be provided. The counter array may include a controller and a plurality of counter units. The controller may output an operation control signal and a direction indication signal. The counter units hold previous output values or may perform a counting operation in response to the operation control signal and may perform an up-count operation or a down-count operation in response to the direction indication signal when performing the counting operation.
摘要翻译：可以提供一种计数器阵列和包括该计数器阵列的图像传感器。计数器阵列可以包括控制器和多个计数器单元。控制器可以输出操作控制信号和方向指示信号。计数器单元保持以前的输出值，或者可以响应于操作控制信号执行计数操作，并且可以在执行计数操作时响应于方向指示信号执行向上计数操作或递减计数操作。

13. 发明申请

US20090084941A1 COUNTER CIRCUIT, AD CONVERSION METHOD, AD CONVERTER, SEMICONDUCTOR DEVICE FOR DETECTING DISTRIBUTION OF PHYSICAL QUANTITIES, AND ELECTRONIC APPARATUS 有权
标题翻译：计数器电路，AD转换方法，AD转换器，用于检测物理分布分布的半导体器件和电子设备
公开(公告)号：US20090084941A1
公开(公告)日：2009-04-02
申请号：US12329682
申请日：2008-12-08
申请人： Yoshinori Muramatsu , Noriyuki Fukushima , Yoshikazu Nitta , Yukihiro Yasui
发明人： Yoshinori Muramatsu , Noriyuki Fukushima , Yoshikazu Nitta , Yukihiro Yasui
IPC分类号： H01L27/02
CPC分类号： H03K23/62 , H03K23/56 , H03M1/1023 , H03M1/123 , H03M1/1295 , H03M1/56 , H04N5/335
摘要： A solid-state image pick up device including a pixel array unit having unit pixels arranged in a matrix pattern. Each unit pixel includes a photoelectric converter. Additionally, the solid-state image pick up device has column signal lines that correspond to the respective columns of the matrix pattern, a row scanning means for selectively controlling each unit pixel, and an analog-digital converting unit for converting analog signals output from the unit pixels in a row selectively controlled by the row scanning means. The analog-digital converting unit further includes an asynchronous counter which performs counting in two modes and the asynchronous counter includes a counter processor configured so that when switching between the count modes occurs, a running count value is broken and there is an interval between the count modes and when a mode begins the running count value is reset to the value before the running count value was broken.
摘要翻译：一种固态图像拾取装置，包括具有以矩阵图案排列的单位像素的像素阵列单元。每个单位像素包括光电转换器。此外，固态图像拾取装置具有与矩阵图案的各列相对应的列信号线，用于选择性地控制每个单位像素的行扫描装置，以及用于转换从单元像素输出的模拟信号的模拟数字转换单元由行扫描装置选择性地控制的行中的单位像素。模拟数字转换单元还包括以两种模式执行计数的异步计数器，并且异步计数器包括配置为当在计数模式之间切换时发生计数模式的计数器处理器，运行计数值被破坏并且计数之间存在间隔模式，当模式开始时，运行计数值将重置为运行计数值中断之前的值。

14. 发明授权

US07272027B2 Priority circuit for content addressable memory 有权
标题翻译：内容可寻址存储器的优先级电路
公开(公告)号：US07272027B2
公开(公告)日：2007-09-18
申请号：US10789299
申请日：2004-02-26
申请人： Jose P. Pereira , Rupesh Ranen Roy , Varadarajan Srinivasan , Sandeep Khanna , Bindiganavale S. Nataraj
发明人： Jose P. Pereira , Rupesh Ranen Roy , Varadarajan Srinivasan , Sandeep Khanna , Bindiganavale S. Nataraj
IPC分类号： G11C15/00
CPC分类号： G11C8/04 , G11C15/04 , H03K3/356139 , H03K23/56
摘要： A digital signal processor having priority logic coupled to an array of storage elements, the priority logic to provide to a priority signal lines an indication of a location of a particular number in the array of storage elements. The priority logic includes compare circuits where each compare circuit is coupled to one of the storage elements in the array of storage elements. Each compare circuit has a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the priority signal lines. The priority logic also includes a delay circuit coupled to each of the compare circuits.
摘要翻译：具有耦合到存储元件阵列的优先级逻辑的数字信号处理器，优先级逻辑用于向优先级信号线提供存储元件阵列中特定数字的位置的指示。优先级逻辑包括比较电路，其中每个比较电路耦合到存储元件阵列中的一个存储元件。每个比较电路具有耦合到存储元件的第一输入，耦合到匹配线的第二输入以及耦合到优先级信号线之一的输入/输出线。优先级逻辑还包括耦合到每个比较电路的延迟电路。

15. 发明申请

US20060280193A1 METHOD AND APPARATUS FOR PERFORMING PACKET CLASSIFICATION FOR POLICY-BASED PACKET ROUTING 审中-公开
标题翻译：用于执行基于策略的分组路由的分组分类的方法和装置
公开(公告)号：US20060280193A1
公开(公告)日：2006-12-14
申请号：US11466395
申请日：2006-08-22
申请人： Varadarajan Srinivasan , Bindiganavale Nataraj , Sandeep Khanna
发明人： Varadarajan Srinivasan , Bindiganavale Nataraj , Sandeep Khanna
IPC分类号： H04L12/56
CPC分类号： H03K3/356139 , G11C8/04 , G11C15/04 , H03K23/56
摘要： A method and apparatus for performing packet classification in a digital signal processor for policy-based packet routing. For one embodiment, the digital signal processor includes a policy statement table for storing policy statements. Each policy statement has associated with it a priority number that indicates the priority of the policy statement relative to other policy statements. The priority numbers are separately stored in a priority index table. The priority index table includes priority logic that determines the most significant priority number from among the policy statements that match an incoming packet during a classification of filter operation. The priority logic also identifies the location in the priority index table of the most significant priority number. The identified location in the priority index table can be used to access associated route information or other information stored in a route memory array. New policy statements can be added at any location in the policy statement table, and the associated priority numbers loaded into corresponding locations in the priority index table. Priority numbers of previously stored priority policy statements may be updated such that the new policy statement does not have the same priority number as the previously stored policy statements.
摘要翻译：一种用于在用于基于策略的分组路由选择的数字信号处理器中执行分组分类的方法和装置。对于一个实施例，数字信号处理器包括用于存储策略语句的策略语句表。每个策略语句与其相关联的优先级数字表示策略语句相对于其他策略语句的优先级。优先级号分别存储在优先级索引表中。优先级索引表包括在过滤器操作分类期间确定与输入分组匹配的策略语句中的最高优先级数的优先级逻辑。优先级逻辑还标识优先级索引表中最重要优先级数的位置。优先级索引表中的识别位置可用于访问存储在路由存储器阵列中的相关联的路由信息或其他信息。可以在策略语句表中的任何位置添加新的策略语句，并将相关的优先级编号加载到优先级索引表中的相应位置。可以更新先前存储的优先级策略语句的优先级数，使得新的策略语句不具有与先前存储的策略语句相同的优先级编号。

16. 发明授权

US07143231B1 Method and apparatus for performing packet classification for policy-based packet routing 失效
标题翻译：用于基于策略的分组路由执行分组分类的方法和装置
公开(公告)号：US07143231B1
公开(公告)日：2006-11-28
申请号：US09406170
申请日：1999-09-23
申请人： Varadarajan Srinivasan , Bindiganavale S. Nataraj , Sandeep Khanna
发明人： Varadarajan Srinivasan , Bindiganavale S. Nataraj , Sandeep Khanna
IPC分类号： G06F12/00
CPC分类号： H03K3/356139 , G11C8/04 , G11C15/04 , H03K23/56
摘要： A method and apparatus for performing packet classification in a digital signal processor for policy-based packet routing. For one embodiment, the digital signal processor includes a policy statement table for storing policy statements. Each policy statement has associated with it a priority number that indicates the priority of the policy statement relative to other policy statements. The priority numbers are separately stored in a priority index table. The priority index table includes priority logic that determines the most significant priority number from among the policy statements that match an incoming packet during a classification of filter operation. The priority logic also identifies the location in the priority index table of the most significant priority number. The identified location in the priority index table can be used to access associated route information or other information stored in a route memory array. New policy statements can be added at any location in the policy statement table, and the associated priority numbers loaded into corresponding locations in the priority index table. Priority numbers of previously stored priority policy statements may be updated such that the new policy statement does not have the same priority number as the previously stored policy statements.
摘要翻译：一种用于在用于基于策略的分组路由选择的数字信号处理器中执行分组分类的方法和装置。对于一个实施例，数字信号处理器包括用于存储策略语句的策略语句表。每个策略语句与其相关联的优先级数字表示策略语句相对于其他策略语句的优先级。优先级号分别存储在优先级索引表中。优先级索引表包括在过滤器操作分类期间确定与输入分组匹配的策略语句中的最高优先级数的优先级逻辑。优先级逻辑还标识优先级索引表中最重要优先级数的位置。优先级索引表中的识别位置可用于访问存储在路由存储器阵列中的相关联的路由信息或其他信息。可以在策略语句表中的任何位置添加新的策略语句，并将相关的优先级编号加载到优先级索引表中的相应位置。可以更新先前存储的优先级策略语句的优先级数，使得新的策略语句不具有与先前存储的策略语句相同的优先级编号。

17. 发明授权

US06757779B1 Content addressable memory with selectable mask write mode 有权
标题翻译：内容可寻址存储器，可选择掩模写入模式
公开(公告)号：US06757779B1
公开(公告)日：2004-06-29
申请号：US09999800
申请日：2001-10-31
申请人： Bindiganavale S. Nataraj , Nilesh A. Gharia , Rupesh R. Roy , Jose P. Pereira , Varadarajan Srinivasan , Sandeep Khanna , Hok F. Wong
发明人： Bindiganavale S. Nataraj , Nilesh A. Gharia , Rupesh R. Roy , Jose P. Pereira , Varadarajan Srinivasan , Sandeep Khanna , Hok F. Wong
IPC分类号： G06F1200
CPC分类号： G06F17/30982 , G11C8/04 , G11C15/00 , G11C15/04 , H03K3/356139 , H03K23/56
摘要： A content addressable memory (CAM) that includes a CAM array and a write circuit. The write circuit is coupled the CAM array and has a coding circuit to convert a first value into a second value, and a select circuit to select either the first value or the second value to be stored in the CAM array.
摘要翻译：内容可寻址存储器（CAM），其包括CAM阵列和写入电路。写入电路与CAM阵列耦合，并具有将第一值转换为第二值的编码电路，以及选择要存储在CAM阵列中的第一值或第二值的选择电路。

18. 发明授权

US5210776A Counter circuit for controlling an absolute position of a robot system 失效
标题翻译：用于控制机器人系统的绝对位置的计数器电路
公开(公告)号：US5210776A
公开(公告)日：1993-05-11
申请号：US774305
申请日：1991-10-10
申请人： Sung-Kwon Kim , Hak-Seo Oh
发明人： Sung-Kwon Kim , Hak-Seo Oh
IPC分类号： B25J9/10 , G05B15/02 , G05B19/21 , G05B19/414 , H03K23/56
CPC分类号： H03K23/56 , G05B19/21 , G05B19/4142 , G05B2219/31137 , G05B2219/33187 , G05B2219/34215 , G05B2219/37154 , G05B2219/41243 , G05B2219/50042
摘要： The present invention relates to a counter circuit for counting the rotated position of the motor and controlling absolute position of the same to control an absolute position of a robot system, which comprises, a RS-422 receiver for receiving encode signals from a motor driver, a 16-bit counter device for receiving rotated-number data of the motor supplied from the receiver and counting the data to output the counted value to a CPU via a bus line, a plurality of 4-bit counters for counting the signals when overflow or underflow is produced at the 16-bit counter portion, a first 8-bit latch circuit for receiving the counted values from the 4-bit counters and outputting the counted values to the CPU, and, a second 8-bit latch circuit for controlling the output state of the receiver on the basis of a control signal supplied through the bus line when a zero pulse control signal is inputted for searching an origin of the robot system thereby preventing erroneous counting operations due to a program and reducing the program porforming time.
摘要翻译：本发明涉及一种计数电路，用于对电动机的旋转位置进行计数，并控制其绝对位置以控制机器人系统的绝对位置，其包括：用于接收来自电机驱动器的编码信号的RS-422接收器， 16位计数器装置，用于接收从接收器提供的电动机的旋转数字数据，并对数据进行计数，以便通过总线将计数值输出到CPU;多个4位计数器，用于在溢出时对信号进行计数; 在16位计数器部分产生下溢，第一8位锁存电路用于接收来自4位计数器的计数值并将计数值输出到CPU，以及第二8位锁存电路，用于控制当输入零脉冲控制信号以搜索机器人系统的原点时，基于通过总线提供的控制信号的接收器的输出状态，从而防止由于一个程序，减少程序的成型时间。

19. 发明授权

US4856035A CMOS binary up/down counter 失效
标题翻译： CMOS二进制加/减计数器
公开(公告)号：US4856035A
公开(公告)日：1989-08-08
申请号：US199831
申请日：1988-05-26
申请人： Edward T. Lewis
发明人： Edward T. Lewis
IPC分类号： G06F7/62 , H03K3/037 , H03K3/356 , H03K23/00 , H03K23/52 , H03K23/56
CPC分类号： H03K23/56 , H03K23/52 , H03K3/037 , H03K3/35606 , H03K3/356078
摘要： A high speed CMOS binary up/down counter having a 200 MHZ clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. The counter performs in an up-count mode or a down-count mode in accordance with the state of a mode select signal. Each stage of the 4-bit counting section comprises a propagate/kill/generate gate for determining the status of a carry signal to a next stage, except the last stage of a 4-bit section, which does not require such a gate because it is coupled to a carry-forward generator along with the outputs from the other preceeding stages in the section. Each 4-bit section performs the counting function through a successive process of modulo-two sums of a lower order carry and the current state of a counter stage without the need for cumbersome gating structures.

20. 发明授权

US07246198B2 Content addressable memory with programmable word width and programmable priority 有权
标题翻译：内容可寻址存储器，具有可编程字宽和可编程优先级
公开(公告)号：US07246198B2
公开(公告)日：2007-07-17
申请号：US11154066
申请日：2005-06-15
申请人： Bindiganavale S. Nataraj , Nilesh A. Gharia , Rupesh R. Roy , Jose P. Pereira , Varadarajan Srinivasan , Sandeep Khanna , Hok F. Wong
发明人： Bindiganavale S. Nataraj , Nilesh A. Gharia , Rupesh R. Roy , Jose P. Pereira , Varadarajan Srinivasan , Sandeep Khanna , Hok F. Wong
IPC分类号： G06F13/00
CPC分类号： G11C15/04 , G06F17/30982 , G11C8/04 , G11C15/00 , H03K3/356139 , H03K23/56
摘要： A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.
摘要翻译：包括CAM阵列和优先级索引表的内容可寻址存储器（CAM）装置。 CAM阵列具有多行CAM单元，每行包括多个行段，并且适于存储跨越可选数量的行段的数据字。优先权索引表耦合到多个CAM单元行，并且适于存储多个优先级数，每个优先级数表示存储在CAM阵列中的相应数据字的优先级。

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