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11. 发明申请

US20160254793A1 CLOCK AND DATA DRIVERS WITH ENHANCED TRANSCONDUCTANCE AND SUPPRESSED OUTPUT COMMON-MODE 审中-公开
标题翻译：具有增强的交叉和抑制输出通用模式的时钟和数据驱动器
公开(公告)号：US20160254793A1
公开(公告)日：2016-09-01
申请号：US15029777
申请日：2014-11-05
申请人： Wenjun SU , Guangming YIN , Quanqing ZHU , QUALCOMM INCORPORATED
发明人： Wenjun SU , Guangming YIN , Quanqing ZHU
IPC分类号： H03F3/45 , H03K5/12
CPC分类号： H03F3/45762 , H03F1/0277 , H03F3/211 , H03F3/45183 , H03F3/45609 , H03F3/72 , H03F2200/555 , H03F2200/72 , H03F2203/45288 , H03F2203/45301 , H03F2203/45511 , H03F2203/45638 , H03F2203/45644 , H03F2203/45702 , H03K5/12
摘要： Methods, apparatus, and means for maintaining a low output common-mode voltage in a driver are provided. One example apparatus includes a first differential amplifier stage configured to provide a differential output for the apparatus; and a second differential amplifier stage configured to drive the first differential amplifier stage, the second differential amplifier stage including a pair of pre-driver amplifiers, a pair of n-stage circuits, and an input skew averaging circuit, wherein each of the pair of n-stage units is split into two half blocks. The input skew averaging circuit is configured to suppress the output common-mode voltage by driving the blocks with complementary digital inputs to average out a skew in a gate-to-source voltage of the pair of n-stage circuits. For certain aspects, two feed-forward capacitors may be added to enhance the transconductance and operating speed of main transistors of the first differential amplifier stage.
摘要翻译：提供了用于在驱动器中维持低输出共模电压的方法，装置和装置。一个示例性设备包括：第一差分放大器级，被配置为提供用于该设备的差分输出; 以及第二差分放大器级，被配置为驱动所述第一差分放大器级，所述第二差分放大器级包括一对预驱动器放大器，一对n级电路和输入偏差平均电路，其中， n级单元分为两个半块。输入偏斜平均电路被配置为通过用互补数字输入驱动块来抑制输出共模电压，以平均一对n级电路的栅极至源极电压的偏移。对于某些方面，可以添加两个前馈电容器以增强第一差分放大器级的主晶体管的跨导和工作速度。

12. 发明授权

US09407259B2 Driver circuit 有权
标题翻译：驱动电路
公开(公告)号：US09407259B2
公开(公告)日：2016-08-02
申请号：US14317190
申请日：2014-06-27
申请人： FINISAR CORPORATION
发明人： Arik Zafrany , Georgios Kalogerakis
IPC分类号： H03B1/00 , H03K3/00 , H03K17/687 , H03F3/45 , H01S5/042 , H04B10/50
CPC分类号： H03K17/6871 , H01S5/042 , H01S5/0427 , H03F3/45085 , H03F3/45179 , H03F3/45282 , H03F2203/45288 , H03F2203/45301 , H03F2203/45554 , H03F2203/45562 , H03F2203/45598 , H03F2203/45702 , H04B10/502 , H04B10/503
摘要： A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.
摘要翻译：电路可以包括第一和第二输入节点，第一和第二输出节点，第一和第二中间节点，第一和第二电阻，耦合到第一输入节点的第一放大晶体管，第一电阻和第一中间节点，耦合到第二输入节点的放大晶体管，第二电阻和第二中间节点。电路还可以包括耦合到第一输出节点和第一中间节点的第一有源器件，耦合到第二输出节点和第二中间节点的第二有源器件，耦合到第一输出节点的第一有效器件，基于第二中间节点上的第二中间信号的行为，以及耦合到第二输出节点并被配置为基于第一中间节点上的第一中间信号进行的第二输出晶体管。

13. 发明授权

US09318184B2 Signal receiver 有权
标题翻译：信号接收机
公开(公告)号：US09318184B2
公开(公告)日：2016-04-19
申请号：US14339811
申请日：2014-07-24
申请人： MStar Semiconductor, Inc.
发明人： Eer-Wen Tyan , Yu-Chieh Hung , Jian-Feng Shiu , Chao-An Chen
IPC分类号： H03K19/0175 , H03K19/094 , G11C11/4076 , H03F3/21 , H03F3/45 , G11C7/10
CPC分类号： G11C11/4076 , G11C7/1084 , H03F3/211 , H03F3/45188 , H03F2203/45702
摘要： A signal receiver includes a current source providing a current having a current value, a pair of active input devices, and a pair of resistors. Each active input device includes a control node, a first conduction node, and a second conduction node. One of the control nodes receives an input signal. The first conduction nodes are connected to each other and receive the current. One of the second conduction nodes serves as an output node. The active input devices output an output signal to a core circuit according to the current and the input signal. Each resistor has a resistance value. A target voltage value is determined according to the resistance value and the current value, such that a voltage swing of the output signal is limited within the target voltage value, and an operating voltage of the core circuit is substantially equal to the target voltage value.
摘要翻译：信号接收机包括提供具有电流值的电流的电流源，一对有源输入装置和一对电阻器。每个有源输入设备包括控制节点，第一传导节点和第二传导节点。一个控制节点接收输入信号。第一传导节点彼此连接并接收电流。第二传导节点之一用作输出节点。有源输入装置根据电流和输入信号将输出信号输出到核心电路。每个电阻都有一个电阻值。根据电阻值和电流值来确定目标电压值，使得输出信号的电压摆幅被限制在目标电压值内，并且核心电路的工作电压基本上等于目标电压值。

14. 发明授权

US09281785B2 Low-noise amplifier, receiver, method and computer program 有权
标题翻译：低噪声放大器，接收器，方法和计算机程序
公开(公告)号：US09281785B2
公开(公告)日：2016-03-08
申请号：US14236972
申请日：2012-07-10
申请人： Henrik Sjöland
发明人： Henrik Sjöland
IPC分类号： H03F1/56 , H03F3/19 , H03F3/45 , H03F1/30 , H03F3/193
CPC分类号： H03F1/56 , H03F1/303 , H03F3/19 , H03F3/193 , H03F3/45071 , H03F3/45098 , H03F3/45183 , H03F3/45197 , H03F2200/222 , H03F2200/294 , H03F2200/447 , H03F2200/451 , H03F2200/468 , H03F2203/45458 , H03F2203/45461 , H03F2203/45464 , H03F2203/45488 , H03F2203/45544 , H03F2203/45554 , H03F2203/45562 , H03F2203/45622 , H03F2203/45638 , H03F2203/45702
摘要： A differential cross-coupled common-source or common-emitter low-noise amplifier having capacitive degeneration is disclosed. Further, a radio receiver comprising such a low-noise amplifier is disclosed. Further, a method of controlling switched capacitive networks of an amplifier is disclosed. The method comprises controlling capacitances of the switched degeneration capacitor networks and/or the switched cross-coupling capacitor networks. Further, a computer program for implementing the method is disclosed.
摘要翻译：公开了具有电容变性的差分交叉耦合共源或共发射极低噪声放大器。此外，公开了一种包括这种低噪声放大器的无线电接收机。此外，公开了一种控制放大器的开关电容网络的方法。该方法包括控制开关退化电容器网络和/或开关交叉耦合电容器网络的电容。此外，公开了一种用于实现该方法的计算机程序。

15. 发明授权

US09246484B2 Apparatus and methods for input bias current reduction 有权
标题翻译：输入偏置电流降低的装置和方法
公开(公告)号：US09246484B2
公开(公告)日：2016-01-26
申请号：US14201234
申请日：2014-03-07
申请人： Analog Devices, Inc.
发明人： Yoshinori Kusuda
IPC分类号： G05F1/10 , H03K17/16 , H03M1/66
CPC分类号： H03F1/0205 , H03F3/387 , H03F3/45179 , H03F3/45183 , H03F3/45556 , H03F2203/45044 , H03F2203/45454 , H03F2203/45466 , H03F2203/45544 , H03F2203/45562 , H03F2203/45604 , H03F2203/45606 , H03F2203/45702 , H03K17/162 , H03M1/66
摘要： Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal.
摘要翻译：本文提供了用于减小电子电路的输入偏置电流的装置和方法。在某些实施方式中，电子电路包括第一输入端，第二输入端，输入电路以及包括至少第一输入开关和第二输入开关的多个输入开关。第一输入开关电连接在第一输入端和输入电路的第一输入端之间，第二输入开关电连接在第二输入端和输入电路的第二输入端之间，第一和第二输入开关可以使用时钟信号打开和关闭。电子电路还包括电荷补偿电路，用于在时钟信号转变期间补偿通过第一和第二输入开关的电荷注入。

16. 发明授权

US09236466B1 Analog circuits having improved insulated gate transistors, and methods therefor 有权
标题翻译：具有改进的绝缘栅晶体管的模拟电路及其方法
公开(公告)号：US09236466B1
公开(公告)日：2016-01-12
申请号：US13646506
申请日：2012-10-05
申请人： MIE Fujitsu Semiconductor Limited
发明人： Sang-Soo Lee , Heetae Ahn , Augustine Kuo
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/823892 , H01L29/105 , H01L29/1083 , H01L29/1087 , H01L29/6659 , H01L29/7833 , H01L29/7838 , H03F3/45183 , H03F3/45197 , H03F2200/555 , H03F2203/45342 , H03F2203/45631 , H03F2203/45674 , H03F2203/45701 , H03F2203/45702
摘要： A circuit can include at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and a bias circuit configured to provide bias currents to the drains of the DDC transistors; wherein each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the first conductivity type formed below the channel region.
摘要翻译：电路可以包括至少一对具有通常耦合到相同电流路径的源的深耗尽通道（DDC）晶体管; 以及偏置电路，被配置为向所述DDC晶体管的漏极提供偏置电流; 其中每个DDC晶体管包括掺杂到第一导电类型的源极和漏极，基本上未掺杂的沟道区，以及形成在沟道区下面的第一导电类型的高掺杂屏蔽区。

17. 发明授权

US09209789B1 Apparatus to convert electrical signals from small-signal format to rail-to-rail format 有权
标题翻译：将电信号从小信号格式转换为轨到轨格式的装置
公开(公告)号：US09209789B1
公开(公告)日：2015-12-08
申请号：US14459168
申请日：2014-08-13
申请人： QUALCOMM Incorporated
发明人： Miao Li , Xiaohua Kong , Dong Ren
IPC分类号： H03L5/00 , H03K5/02 , H03K19/0175
CPC分类号： H03F3/505 , H03F1/0272 , H03F3/45183 , H03F3/4565 , H03F3/45708 , H03F2200/453 , H03F2200/78 , H03F2203/45292 , H03F2203/45416 , H03F2203/45418 , H03F2203/45424 , H03F2203/45594 , H03F2203/45604 , H03F2203/45664 , H03F2203/45702 , H04L25/0276
摘要： Techniques for converting a signal from a small-signal format into a rail-to-rail format are described herein. In one embodiment, a receiver comprises a voltage-level shifter configured to shift a common-mode voltage of a differential signal to obtain a level-shifted differential signal, an amplifier configured to amplify the level-shifted differential signal into an amplified differential signal, and a driver stage configured to convert the amplified differential signal into a rail-to-rail signal. The receiver also comprises a common-mode feedback circuit configured to generate a feedback voltage that is proportional to an output common-mode voltage of the amplifier, and to generate a bias voltage for input to the amplifier based on a difference between the feedback voltage and a reference voltage, wherein the output common-mode voltage of the amplifier depends on the bias voltage.
摘要翻译：这里描述了用于将信号从小信号格式转换为轨到轨格式的技术。在一个实施例中，接收机包括：电压电平移位器，被配置为移位差分信号的共模电压以获得电平移位的差分信号;放大器，被配置为将电平移位的差分信号放大为放大的差分信号，以及驱动器级，被配置为将放大的差分信号转换成轨到轨信号。接收机还包括共模反馈电路，其被配置为产生与放大器的输出共模电压成比例的反馈电压，并且基于反馈电压和反馈电压之间的差产生用于输入到放大器的偏置电压参考电压，其中放大器的输出共模电压取决于偏置电压。

18. 发明申请

US20150341004A1 DIFFERENTIAL AMPLIFICATION CIRCUIT 有权
标题翻译：差分放大电路
公开(公告)号：US20150341004A1
公开(公告)日：2015-11-26
申请号：US14631582
申请日：2015-02-25
申请人： FUJITSU LIMITED
发明人： Kazuaki OISHI
IPC分类号： H03F3/45 , H03F1/02
CPC分类号： H03F3/45179 , H03F1/0211 , H03F1/0272 , H03F3/45085 , H03F3/45197 , H03F3/45659 , H03F3/45748 , H03F2200/144 , H03F2203/45118 , H03F2203/45418 , H03F2203/45434 , H03F2203/45481 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528 , H03F2203/45631 , H03F2203/45694 , H03F2203/45702
摘要： A differential amplification circuit includes: a first input node; a second input node; a first output node; a second output node; a first transistor having a gate coupled to the first input node and a source coupled to a first node; a second transistor having a gate coupled to the second input node; a third transistor having a drain coupled to a drain of the first transistor; a fourth transistor having a gate coupled to a gate of the third transistor; a first resistor; a second resistor; a fifth transistor having a gate coupled to the drain of the first transistor; a sixth transistor having a gate coupled to the drain of the second transistor; a seventh transistor having a source coupled to the first node; an eighth transistor having a gate coupled to a gate of the seventh transistor; a third resistor; and a fourth resistor.
摘要翻译：差分放大电路包括：第一输入节点; 第二输入节点; 第一输出节点; 第二输出节点; 第一晶体管，具有耦合到第一输入节点的栅极和耦合到第一节点的源极; 第二晶体管，具有耦合到第二输入节点的栅极; 第三晶体管，具有耦合到所述第一晶体管的漏极的漏极; 第四晶体管，具有耦合到第三晶体管的栅极的栅极; 第一个电阻; 第二电阻器; 第五晶体管，具有耦合到第一晶体管的漏极的栅极; 第六晶体管，其具有耦合到所述第二晶体管的漏极的栅极; 第七晶体管，具有耦合到所述第一节点的源极; 第八晶体管，具有耦合到第七晶体管的栅极的栅极; 第三电阻; 和第四电阻器。

19. 发明申请

US20150280666A1 DIFFERENTIAL AMPLIFICATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：差分放大电路和半导体集成电路
公开(公告)号：US20150280666A1
公开(公告)日：2015-10-01
申请号：US14626491
申请日：2015-02-19
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Tomoyuki ARAI
IPC分类号： H03G1/00 , H03F3/45
CPC分类号： H03G1/0029 , H03F3/45197 , H03F2203/45494 , H03F2203/45496 , H03F2203/45504 , H03F2203/45702 , H03G1/0088 , H03G3/001 , H03G2201/40
摘要： A differential amplification circuit includes: a first transistor and a second transistor of a differential pair; first and second loads; current sources; and a resistor circuit, wherein the resistor circuit includes: a coarse adjustment part and a fine adjustment part, one of the coarse adjustment part and the fine adjustment part includes a first lateral adjustment part and a second lateral adjustment part which have the same configuration, the first lateral adjustment part and the second lateral adjustment part are connected symmetrically to both sides of a central adjustment part, and the central adjustment part has a circuit configuration symmetrical with respect to two connection nodes with the first lateral adjustment part and the second lateral adjustment part.
摘要翻译：差分放大电路包括：差分对的第一晶体管和第二晶体管; 第一和第二载荷; 当前来源以及电阻电路，其特征在于，所述电阻电路包括：粗调部和微调部，所述粗调部和微调部之一包括具有相同结构的第一横向调整部和第二横向调整部，第一横向调节部分和第二横向调节部分对称地连接到中央调节部分的两侧，并且中央调节部分具有相对于具有第一横向调节部分和第二横向调节部的两个连接节点对称的电路构造部分。

20. 发明授权

US09025709B2 Receiver front-end circuit, communication unit and method therefor 有权
标题翻译：接收机前端电路，通信单元及其方法
公开(公告)号：US09025709B2
公开(公告)日：2015-05-05
申请号：US14221302
申请日：2014-03-21
申请人： Mediatek Inc.
发明人： Chih-Fan Liao , Ming-Da Tsai
IPC分类号： H04B1/10 , H04L1/00
CPC分类号： H04B1/10 , H03F1/3211 , H03F1/3223 , H03F3/195 , H03F3/211 , H03F3/3028 , H03F3/45475 , H03F2200/294 , H03F2200/411 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528 , H03F2203/45594 , H03F2203/45702 , H04L1/0036
摘要： A receiver front end circuit includes a low-noise amplifier including: a first receiver path having: a first low-noise transconductor to amplify a received signal and output the amplified received signal; and a first mixer to down-convert the amplified received signal. A second receiver path includes: an auxiliary receiver having: a second transconductor to output an amplified received signal; a baseband amplifier having an input port and an output port; a first resistance coupling the input port to the output port of the baseband amplifier and to convert the amplified received signal from current to voltage and set a voltage gain of the second receiver path; and a second resistance coupled from the output port of the baseband amplifier to the first mixer output. In some examples, frequency-upconversion feedback path includes a third mixer to frequency up-convert the amplified received signal at an output of the second receiver path.
摘要翻译：接收机前端电路包括低噪声放大器，包括：第一接收器路径，具有：第一低噪声跨导器，用于放大接收信号并输出放大的接收信号; 以及用于对放大的接收信号进行下变频的第一混频器。第二接收机路径包括：辅助接收机，具有：第二跨导体，用于输出放大的接收信号; 具有输入端口和输出端口的基带放大器; 第一电阻将输入端口耦合到基带放大器的输出端口，并将放大的接收信号从电流转换成电压，并设置第二接收器路径的电压增益; 以及从基带放大器的输出端口耦合到第一混频器输出的第二电阻。在一些示例中，上变频反馈路径包括第三混频器，用于在第二接收机路径的输出端对放大的接收信号进行升频转换。

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