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11. 发明授权

US08972652B2 Data refresh in non-volatile memory 有权
标题翻译：非易失性存储器中的数据刷新
公开(公告)号：US08972652B2
公开(公告)日：2015-03-03
申请号：US13680507
申请日：2012-11-19
申请人： Spansion LLC
发明人： Yong K. Kim , Keith H. Wong , Mark A. McClain
IPC分类号： G06F12/00 , G11C16/10 , G11C16/34 , G11C16/02 , G11C16/16
CPC分类号： G11C16/10 , G11C16/02 , G11C16/16 , G11C16/3418
摘要： A method of reducing read errors in a non-volatile memory device that result from bit-line or word-line disturb conditions generated by erase operations includes selecting a subset of a memory array for refresh after each erase operation. A pointer to the refresh target section is updated as part of the method to direct the refresh operation to the appropriate subset of the memory array. Refresh may be performed subsequent to an erase operation or concurrently therewith. By distributing the time consumed by refresh operations over many erase operations so the relative refresh time for any one erase becomes small.
摘要翻译：减少由擦除操作产生的位线或字线干扰条件导致的非易失性存储器件中读取错误的方法包括在每个擦除操作之后选择用于刷新的存储器阵列的子集。指向刷新目标部分的指针被更新为将刷新操作引导到存储器阵列的适当子集的方法的一部分。可以在擦除操作之后或与之同时执行刷新。通过在许多擦除操作上分配刷新操作消耗的时间，使得任何一个擦除的相对刷新时间变小。

12. 发明授权

US08902663B1 Method of maintaining a memory state 有权
标题翻译：保持记忆状态的方法
公开(公告)号：US08902663B1
公开(公告)日：2014-12-02
申请号：US13792202
申请日：2013-03-11
申请人： Monolithic 3D Inc.
发明人： Zvi Or-Bach , Yuniarto Widjaja
IPC分类号： G11C16/04 , G11C16/02
CPC分类号： H01L29/78 , G11C11/404 , G11C11/4097 , G11C11/412 , G11C16/02 , G11C16/0483 , G11C2213/71 , H01L27/10802 , H01L27/1104 , H01L27/115 , H01L27/11578 , H01L27/2436 , H01L29/7841
摘要： A method of maintaining a memory state of a 3D memory, wherein the memory includes at least a first cell and a second cell overlying the first cell, the method including: applying a back-bias to the first cell and the second cell without interrupting data access to the memory, and generating at least two stable floating body charge levels of the memory state.
摘要翻译：一种保持3D存储器的存储状态的方法，其中所述存储器至少包括第一单元和覆盖所述第一单元的第二单元，所述方法包括：将第一单元和所述第二单元的反向偏压应用于中断数据访问存储器，并且产生存储器状态的至少两个稳定的浮动体电荷电平。

13. 发明申请

US20130336070A1 APPARATUSES AND METHODS TO MODIFY PILLAR POTENTIAL 有权
标题翻译：修改支柱潜力的装置和方法
公开(公告)号：US20130336070A1
公开(公告)日：2013-12-19
申请号：US13525035
申请日：2012-06-15
申请人： Koji Sakui , Peter Sean Feeley
发明人： Koji Sakui , Peter Sean Feeley
IPC分类号： G11C16/10 , H01L29/788
CPC分类号： G11C16/10 , G11C16/02 , G11C16/0466 , G11C16/0483
摘要： Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices associated with a pillar, and each pillar including semiconductor material. Methods are disclosed, such as a method that includes performing a first operation on a first charge storage device associated with a pillar in the block, modifying an electrical potential of the pillar, and performing a second operation on a second charge storage device in the block. Additional apparatus and methods are described.
摘要翻译：公开了诸如包括多个电荷存储装置串的块的每个串，包括与柱相关联的多个电荷存储装置，并且每个支柱包括半导体材料。公开了一种方法，例如包括在与块中的柱相关联的第一电荷存储装置上执行第一操作的方法，修改支柱的电位，以及对块中的第二电荷存储装置执行第二操作。描述附加的装置和方法。

14. 发明申请

US20130279268A1 EEPROM CELL WITH STORAGE CAPACITOR 审中-公开
标题翻译：具有存储电容器的EEPROM单元
公开(公告)号：US20130279268A1
公开(公告)日：2013-10-24
申请号：US13653711
申请日：2012-10-17
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH
发明人： Jin-Yeong KANG
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C14/00 , G11C16/02 , H01L27/115
摘要： In an EEPROM cell, as a storage capacitor is added between a control plate and a tunneling plate, after the storage capacitor is charged for a time that is relatively smaller than a time necessary for writing or erasing data of the EEPROM cell, the EEPROM cell that can perform operation of writing or erasing data of the EEPROM cell using a charge voltage that is stored at the storage capacitor is provided. Therefore, operation of writing or erasing data of the EEPROM cell within a short time using the EEPROM cell can be performed, and thus entire productivity of the EEPROM can be improved.
摘要翻译：在EEPROM单元中，由于在控制板和隧道板之间添加了存储电容器，所以在将存储电容器充电至相对小于写入或擦除EEPROM单元数据所需要的时间之前，EEPROM单元提供可以使用存储在存储电容器的充电电压来执行写入或擦除EEPROM单元的数据的操作。因此，可以执行使用EEPROM单元在短时间内写入或擦除EEPROM单元的数据的操作，从而可以提高EEPROM的整体生产率。

15. 发明申请

US20130248960A1 SYSTEM AND METHOD OF UV PROGRAMMING OF NON-VOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器的紫外编程系统与方法
公开(公告)号：US20130248960A1
公开(公告)日：2013-09-26
申请号：US13425451
申请日：2012-03-21
申请人： Hsiang-Tai LU , Chih-Hsien LIN
发明人： Hsiang-Tai LU , Chih-Hsien LIN
IPC分类号： H01L29/788 , H01L21/66 , H01L21/336
CPC分类号： H01L27/11521 , G11C16/02 , G11C16/0416 , G11C16/225 , G11C29/04 , G11C2029/0403 , H01L21/28273 , H01L21/3205 , H01L22/14 , H01L27/11558
摘要： A semiconductor memory storage device includes first and second doped regions of a first type disposed in a semiconductor substrate. The first and second doped regions of the first type being laterally spaced from one another. A gate dielectric extends over the semiconductor substrate between the first and second doped regions, and a floating gate is disposed on the gate dielectric. An ultraviolet (UV) light blocking material is vertically disposed above the floating gate and has a size that covers the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light.
摘要翻译：半导体存储器存储器件包括设置在半导体衬底中的第一类型的第一和第二掺杂区域。第一类型的第一和第二掺杂区域彼此横向间隔开。栅极电介质在第一和第二掺杂区域之间的半导体衬底上延伸，并且浮置栅极设置在栅极电介质上。紫外（UV）遮光材料垂直地设置在浮动栅极上方，并且具有覆盖浮动栅极的尺寸，使得在半导体存储器存储装置暴露于紫外光之后浮置栅极保持充电。

16. 发明授权

US08514609B2 Semiconductor device and method of driving semiconductor device 有权
标题翻译：半导体装置及其驱动方法
公开(公告)号：US08514609B2
公开(公告)日：2013-08-20
申请号：US13019342
申请日：2011-02-02
申请人： Daisuke Kawae , Hideki Uochi
发明人： Daisuke Kawae , Hideki Uochi
IPC分类号： G11C11/24
CPC分类号： G11C11/405 , G11C16/02 , H01L27/105 , H01L27/1052 , H01L27/11521 , H01L27/1156 , H01L27/1203 , H01L27/1225
摘要： The number of wirings per unit memory cell is reduced by sharing a bit line by a writing transistor and a reading transistor. Data is written by turning on the writing transistor so that a potential of the bit line is supplied to a node where one of a source and drain electrodes of the writing transistor and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined amount of charge is held in the node. Data is read by using a signal line connected to a capacitor as a reading signal line or a signal line connected to one of a source and drain electrodes of the reading transistor as a reading signal line so that a reading potential is supplied to the reading signal line, and then detecting a potential of the bit line.
摘要翻译：通过由写入晶体管和读取晶体管共享位线来减少每单位存储单元的布线数量。通过接通写入晶体管来写入数据，使得位线的电位被提供给写入晶体管的源极和漏极之一以及读取晶体管的栅电极之一电连接，然后关断写入晶体管，使得在节点中保持预定量的电荷。通过使用连接到电容器的信号线作为读取信号线或连接到读取晶体管的源极和漏极之一的信号线作为读取信号线来读取数据，使得读取电位被提供给读取信号线，然后检测位线的电位。

17. 发明授权

US08456922B2 Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage 有权
公开(公告)号：US08456922B2
公开(公告)日：2013-06-04
申请号：US13477431
申请日：2012-05-22
申请人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
发明人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
IPC分类号： G11C16/16
CPC分类号： G11C16/14 , G11C16/02 , G11C16/0408 , G11C16/08 , G11C16/16
摘要： A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

18. 发明授权

US08314637B2 Non-volatile latch circuit and logic circuit, and semiconductor device using the same 有权
标题翻译：非易失性锁存电路和逻辑电路，以及使用其的半导体器件
公开(公告)号：US08314637B2
公开(公告)日：2012-11-20
申请号：US12966513
申请日：2010-12-13
申请人： Kiyoshi Kato , Jun Koyama
发明人： Kiyoshi Kato , Jun Koyama
IPC分类号： H01L25/00 , H03K19/00
CPC分类号： H03K19/1733 , G11C14/0063 , G11C16/02 , H01L21/8258 , H01L21/84 , H01L27/0688 , H01L27/088 , H01L27/1156 , H01L27/1203 , H01L27/1225 , H01L29/7869 , H03K3/356008 , H03K3/35606
摘要： A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.
摘要翻译：提供了一种新颖的非易失性锁存电路和使用非易失性锁存电路的半导体器件。锁存电路具有环形结构，其中第一元件的输出电连接到第二元件的输入，并且第二元件的输出通过第二晶体管电连接到第一元件的输入端。使用使用氧化物半导体作为沟道形成区域的半导体材料的晶体管作为开关元件，并且提供电容器以电连接到晶体管的源电极或漏电极，由此锁存电路的数据可以并且可以形成非易失性锁存电路。

19. 发明授权

US08243490B2 Memory with intervening transistor 有权
标题翻译：具有中间晶体管的存储器
公开(公告)号：US08243490B2
公开(公告)日：2012-08-14
申请号：US12627751
申请日：2009-11-30
申请人： Cyrille Dray
发明人： Cyrille Dray
IPC分类号： G11C5/06
CPC分类号： G11C16/02 , G11C8/14
摘要： Disclosed herein are memory devices and related methods and techniques. A cell in the memory device may be associated with an intervening transistor, the intervening transistor being configured to isolate the cell from adjacent cells under a first operating condition and to provide a current to a bit line associated with the cell under a second operating condition.
摘要翻译：这里公开的是存储器件和相关的方法和技术。存储器件中的单元可以与中间晶体管相关联，所述中间晶体管被配置为在第一操作条件下隔离所述单元与相邻单元，并且在第二操作条件下向与所述单元相关联的位线提供电流。

20. 发明申请

US20120155150A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120155150A1
公开(公告)日：2012-06-21
申请号：US13316607
申请日：2011-12-12
申请人： Shuhei Nagatsuka , Yasuyuki Takahashi
发明人： Shuhei Nagatsuka , Yasuyuki Takahashi
IPC分类号： G11C11/24 , G11C8/10
CPC分类号： G11C7/22 , G11C5/06 , G11C8/10 , G11C11/404 , G11C16/02 , H01L27/1052 , H01L27/1156 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L29/7869
摘要： A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.
摘要翻译：具有新颖结构的半导体存储装置，即使在未提供电力（即非易失性）的情况下也可以保留存储的数据，并且对写入周期的数量没有限制。半导体存储装置包括存储单元阵列，其中多个存储单元以矩阵形式排列;解码器，被配置为根据控制信号选择存储单元在多个存储单元之间进行操作;以及控制电路，选择是否将控制信号输出到解码器。在多个存储单元的每一个中，通过关闭其沟道区域形成有氧化物半导体的选择晶体管来保持数据。

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