专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08392491B2 Shift calculator 失效
标题翻译：移位计算器
公开(公告)号：US08392491B2
公开(公告)日：2013-03-05
申请号：US12827569
申请日：2010-06-30
申请人： Kunihiko Tajiri
发明人： Kunihiko Tajiri
IPC分类号： G06F15/00
CPC分类号： G06F5/015
摘要： A shift calculator including a first shifter includes a right shifter configured to perform a right shift of 0 to 3 bits and a left shifter configured to perform a left shift of 0 to 3 bits, on input data of which a data width is N bits, in accordance with left/right selection signals, based on a shift amount of 3 bits or smaller out of an input shift amount, a rotator configured to perform a right rotate shift of 0 to N−4 bits or a left rotate shift of 0 to N−4 bits, on output data from said first shifter, in accordance with said left/right selection signals, based on a shift amount of 4 bits or greater out of the input shift amount, and a mask unit configured to perform mask processing in 4-bit increments on output data from said rotator based on mask signals.
摘要翻译：包括第一移位器的移位计算器包括被配置为执行0到3位的右移位的右移位器和被配置为对数据宽度为N位的输入数据执行0到3位的左移的左移位器，根据左/右选择信号，基于输入移位量的3位或更小的移位量，旋转器被配置为执行0到N-4位的右旋转移位或者向左旋转移位0到根据所述左/右选择信号，根据所述输入移位量中的4位或更大的移位量，对来自所述第一移位器的输出数据的N-4位，以及掩模单元，被配置为执行掩码处理基于掩码信号，来自所述旋转器的输出数据的4位增量。

12. 发明申请

US20130018933A1 Data Shifter and Control Method Thereof, Multiplexer, Data Sifter, and Data Sorter 审中-公开
标题翻译：数据移位器及其控制方法，多路复用器，数据筛选器和数据分类器
公开(公告)号：US20130018933A1
公开(公告)日：2013-01-17
申请号：US13636360
申请日：2010-03-31
申请人： Kazunori Asanaka
发明人： Kazunori Asanaka
IPC分类号： G06F7/00
CPC分类号： G06F7/76 , G06F5/015 , G06F7/24 , G06F7/762
摘要： A data shifter (10) includes plural stages each including N elemental units (20), each preliminarily assigned a one-bit value c and a positive integer q. The mth elemental unit in the pth stage inputs target data and destination data representing a lane number where Data(p,m), a logical OR of the input target data, should be routed to; compares the qth bit from the LSB of Des(p,m), a logical OR of the input destination data, with the c; and outputs, based on the comparison result, both Data(p,m) or the value 0 and Des(p,m) or the value 0 bound for the mth elemental unit in the next stage, and if m−1+2q-1
摘要翻译：数据移位器（10）包括多个级，每级包括N个元件单元（20），每个级分预先分配一位值c和正整数q。第p级的第m个元素单元输入表示通道号的目标数据和目的地数据，其中输入目标数据的逻辑OR应该被路由到数据（p，m）; 将来自Des（p，m）的LSB的输入目的地数据的逻辑或与c的第q位进行比较; 并且基于比较结果输出Data（p，m）或值0和Des（p，m）或下一级中第m个元素单元所绑定的值0，并且如果m-1 + 2q- 1

13. 发明申请

US20120239717A1 FUNNEL SHIFTER IMPLEMENTATION 有权
标题翻译： FUNNEL SHITER实施
公开(公告)号：US20120239717A1
公开(公告)日：2012-09-20
申请号：US13164235
申请日：2011-06-20
申请人： Raymond C. Yeung , Lincoln R. Nunes , Geoffrey F. Oh
发明人： Raymond C. Yeung , Lincoln R. Nunes , Geoffrey F. Oh
IPC分类号： G06F5/01
CPC分类号： G06F5/015
摘要： A funnel shifter includes an input, an output, and a multiplexer unit including a number of multiplexer levels. The multiplexer unit may perform one of a plurality of shift operations on an input value and to provide an output value in response to receiving a shift value and a shift operation value. A first multiplexer level may be configured to format and expand the input value into a larger intermediate value. At least a second multiplexer level may be configured to perform a linear shift of the intermediate value without wrapping any bits for creating the output value. At least some of the multiplexer levels may include multiplexer select signals that may be represented as a plurality of N-Nary one of N signals where N is greater than or equal to two, wherein each of the plurality of N-Nary signals being implemented on a set of physical wires.
摘要翻译：漏斗移位器包括输入，输出和包括多个复用器电平的多路复用器单元。复用器单元可以对输入值执行多个移位操作中的一个，并且响应于接收到移位值和移位操作值而提供输出值。可以将第一多路复用器级配置为将输入值格式化并扩展成更大的中间值。至少第二多路复用器级可以被配置为执行中间值的线性移位，而不包裹用于创建输出值的任何位。多路复用器电平中的至少一些可以包括多路复用器选择信号，其可以被表示为N个信号中的多个N个N个信号，其中N大于或等于2，其中多个N-Nary信号中的每一个被实现在一套物理线。

14. 发明申请

US20110167240A1 Method of rotating data in a plurality of processing elements 有权
公开(公告)号：US20110167240A1
公开(公告)日：2011-07-07
申请号：US13048082
申请日：2011-03-15
申请人： Mark Beaumont
发明人： Mark Beaumont
IPC分类号： G06F15/76 , G06F9/315
CPC分类号： G06F5/015
摘要： A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the shifting and storing operations coordinated to enable a three shears operation to be performed on the data. The plurality of storing operations is responsive to the processing element's positions.

15. 发明授权

US07831652B2 Floating point multiplier with embedded status information 有权
标题翻译：具有嵌入状态信息的浮点乘数
公开(公告)号：US07831652B2
公开(公告)日：2010-11-09
申请号：US10035580
申请日：2001-12-28
申请人： Guy L. Steele, Jr.
发明人： Guy L. Steele, Jr.
IPC分类号： G06F7/44 , G06F7/00
CPC分类号： G06F9/30094 , G06F5/012 , G06F5/015 , G06F7/483 , G06F7/4873 , G06F7/4876 , G06F7/49905 , G06F7/49942 , G06F9/30014 , G06F9/30021 , G06F9/3861 , G06F9/3885
摘要： A system for providing a floating point product comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data within the second floating point operand respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the product of the first floating point operand and the second floating point operand. Additionally, the results circuit provides a resulting status embedded within the resulting floating point operand.
摘要翻译：一种用于提供浮点乘积的系统，包括：分析器电路，被配置为基于所述第一浮点数操作数内的数据和所述第二浮点内的数据来确定第一浮点操作数的第一状态和第二浮点操作数的第二状态操作数。此外，该系统包括耦合到分析器电路的结果电路。结果电路被配置为断言包含第一个浮点数操作数和第二个浮点操作数的积的浮点运算数。另外，结果电路提供嵌入到所得到的浮点运算数中的结果状态。

16. 发明申请

US20090296868A1 Method for Shifting Data Bits Multiple Times Per Clock Cycle 审中-公开
标题翻译：每个时钟周期多次移位数据位的方法
公开(公告)号：US20090296868A1
公开(公告)日：2009-12-03
申请号：US12536186
申请日：2009-08-05
申请人： Hui PAN , Seong-Ho Lee , Michael Q. Le
发明人： Hui PAN , Seong-Ho Lee , Michael Q. Le
IPC分类号： H04L7/00
CPC分类号： G06F5/015 , G06F5/017 , G11C19/00
摘要： A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.
摘要翻译：使用一种系统和方法来允许产生相位旋转器控制信号，其中每个时钟周期使信号中的位数超过一个步长。这可以通过以下操作完成。存储包括多个数据位的第一和第二数据信号。在每个时钟周期期间，基于相位控制信号来控制第一数据信号中的数据比特和随后的第二数据信号中的数据比特的旋转。第一和第二受控数据信号被交织以形成第一和第二交错数据信号。在时钟周期的后半段期间，基于相位控制信号的一部分来选择第一和第二交错数据信号中的一个。最后，选择的数据信号作为相位控制信号发送。

17. 发明授权

US07461108B2 Barrel shift device 失效
标题翻译：桶式换档装置
公开(公告)号：US07461108B2
公开(公告)日：2008-12-02
申请号：US10578780
申请日：2005-08-31
申请人： Kazufumi Tanoue , Daisuke Takeuchi , Tomoko Chiba
发明人： Kazufumi Tanoue , Daisuke Takeuchi , Tomoko Chiba
IPC分类号： G06F7/00
CPC分类号： G06F5/015
摘要： When a barrel shift device is divided into pipeline registers and a shift process is executed in a multistage process stage, by decoding a second control signal for controlling a shift amount of a second shift circuit 50 using a decoding circuit 20, it is detected at what digit positions in intermediate data in an intermediate data holding circuit 30 data elements which are to be finally output as output data from the second shift circuit 50 are located. Based on a result of the detection of digit positions by the decoding circuit 20, the intermediate data holding circuit 30 holds only data elements to be finally output, among data elements in the intermediate data, and does not hold unnecessary data elements which are not included in the output data. Therefore, by controlling a data storage operation in the intermediate data holding circuit 30, an increase in power due to the pipeline structure is suppressed.
摘要翻译：当桶式换档装置被分成流水线寄存器并且在多级处理级中执行移位处理时，通过使用解码电路20对用于控制第二移位电路50的移位量的第二控制信号进行解码，在中间数据保持电路中的中间数据中的数字位置30位于最终作为来自第二移位电路50的输出数据输出的数据元素。基于由解码电路20检测到数字位置的结果，中间数据保持电路30仅保存中间数据中的数据元素中最终输出的数据元素，并且不保存不包括的不必要的数据元素在输出数据中。因此，通过控制中间数据保持电路30中的数据存储操作，抑制了由于管道结构引起的功率的增加。

18. 发明申请

US20070180007A1 Barrel shift device 失效
标题翻译：桶式换档装置
公开(公告)号：US20070180007A1
公开(公告)日：2007-08-02
申请号：US10578780
申请日：2005-08-31
申请人： Kazufumi Tanoue , Daisuke Takeuchi , Tomoko Chiba
发明人： Kazufumi Tanoue , Daisuke Takeuchi , Tomoko Chiba
IPC分类号： G06F7/00
CPC分类号： G06F5/015
摘要： When a barrel shift device is divided into pipeline registers and a shift process is executed in a multistage process stage, by decoding a second control signal for controlling a shift amount of a second shift circuit 50 using a decoding circuit 20, it is detected at what digit positions in intermediate data in an intermediate data holding circuit 30 data elements which are to be finally output as output data from the second shift circuit 50 are located. Based on a result of the detection of digit positions by the decoding circuit 20, the intermediate data holding circuit 30 holds only data elements to be finally output, among data elements in the intermediate data, and does not hold unnecessary data elements which are not included in the output data. Therefore, by controlling a data storage operation in the intermediate data holding circuit 30, an increase in power due to the pipeline structure is suppressed.
摘要翻译：当桶式换档装置被分成流水线寄存器并且在多级处理级中执行移位处理时，通过使用解码电路20对用于控制第二移位电路50的移位量的第二控制信号进行解码，在中间数据保持电路中的中间数据中的数字位置30位于最终作为来自第二移位电路50的输出数据输出的数据元素。基于由解码电路20检测到数字位置的结果，中间数据保持电路30仅保存中间数据中的数据元素中最终输出的数据元素，并且不保存不包括的不必要的数据元素在输出数据中。因此，通过控制中间数据保持电路30中的数据存储操作，抑制了由于管道结构引起的功率的增加。

19. 发明申请

US20060206548A1 Comparator unit for comparing values of floating point operands 有权
公开(公告)号：US20060206548A1
公开(公告)日：2006-09-14
申请号：US11394081
申请日：2006-03-31
申请人： Guy Steele
发明人： Guy Steele
IPC分类号： G06F15/00
CPC分类号： G06F5/012 , G06F5/015 , G06F7/026 , G06F7/483 , G06F7/4873 , G06F7/4876 , G06F7/49905 , G06F9/30014 , G06F9/30021 , G06F9/30094 , G06F9/3861 , G06F9/3885
摘要： A floating point comparator circuit for comparing a plurality of floating point operands includes a plurality of analysis circuits, one for each of the floating point operands, configured to determine a format of each of the floating point operands based upon floating point status information encoded within each of the floating point operands, and a result generator circuit coupled to the analysis circuits, the result generator circuit configured to generate a result signal based on the format determined by each analysis circuit and based on a comparative relationship among the floating point operands. The format of each of the floating point operands may be from a group comprising: not-a-number (NaN), infinity, normalized, denormalized, zero, invalid operation, overflow, underflow, division by zero, exact, and inexact. The result generator circuit may ignore the encoded floating point statuses of the plurality of floating point operands when comparing just the magnitudes of the plurality of floating point operands.

20. 发明授权

US07016928B2 Floating point status information testing circuit 有权
公开(公告)号：US07016928B2
公开(公告)日：2006-03-21
申请号：US10035741
申请日：2001-12-28
申请人： Guy L. Steele, Jr.
发明人： Guy L. Steele, Jr.
IPC分类号： G06F7/00
CPC分类号： G06F7/483 , G06F5/012 , G06F5/015 , G06F7/4873 , G06F7/4876 , G06F7/49905 , G06F9/30014 , G06F9/30021 , G06F9/30094 , G06F9/3861 , G06F9/3885
摘要： A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point operand based upon data within the operand. An operand buffer may supply the operand to the analysis circuit. The result generator circuit is responsive to at least one control signal and asserts a result signal if the floating point analysis circuit matches the floating point status to a predetermined format specified by the control signal. The result signal can condition the outcome of a floating point instruction. The result generator may also respond to multiple control signals asserted when testing a single operand for different formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, exact, and inexact.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式