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    • 13. 发明授权
    • Automatic adjustment circuit for amplitude of differential signal
    • 差分信号振幅自动调整电路
    • US07831223B2
    • 2010-11-09
    • US11848918
    • 2007-08-31
    • Yutaka Kawashima
    • Yutaka Kawashima
    • H04B17/00
    • H04L1/0002
    • An automatic adjustment circuit for amplitude of differential signal has a differential signal transceiver that transmits differential signals, an amplitude setting register in which plural setting values for setting amplitude of the differential signals are stored, an amplitude control circuit that controls the amplitude of the differential signals, a pattern generating circuit that outputs a test pattern, a multiplexer, a squelch detection receiver, a test loop-back circuit, a squelch-signal-change-detection expected-value memory that stores an expected value of a change in a squelch signal, a squelch-signal-change detection counter that counts the change in the squelch signal, a comparator that compares the expected value and a count value and outputs a difference value of the values, a comparison result memory that stores the difference value, and a controller.
    • 用于差分信号幅度的自动调节电路具有发送差分信号的差分信号收发器,其中存储用于设置差分信号幅度的多个设定值的幅度设定寄存器,控制差分信号幅度的幅度控制电路 ,输出测试图案的模式产生电路,多路复用器,静噪检测接收器,测试回路电路,静噪信号变化检测预期值存储器,其存储静噪信号中的变化的期望值 对静噪信号的变化进行了计数的静噪信号变化检测计数器,将期望值和计数值进行比较的比较器,输出该值的差分值,存储差分值的比较结果存储器和 控制器。
    • 14. 发明申请
    • BUS ARBITER AND BUS SYSTEM
    • BUS ARBITER和BUS系统
    • US20100153610A1
    • 2010-06-17
    • US12637183
    • 2009-12-14
    • Yutaka Kawashima
    • Yutaka Kawashima
    • G06F13/28G06F13/36
    • G06F13/364
    • A bus interface unit receives first and second data sent out to a data bus and observes address values indicated on an address bus. The first and second data are written into first and second registers respectively. First and second address detection unit receive the address values observed by the bus interface respectively. The first address detection unit outputs a first detection signal when it detects an address value which corresponds with the value of the first data. The second address detection unit outputs a second detection signal, when it detects an address value having an increment from the first data, which corresponds with the value of the second data. A control unit raises the priority of one of the bus masters given a bus utilization right, during the period from a start of outputting the first detection signal to an end of outputting the second detection signal.
    • 总线接口单元接收发送到数据总线的第一和第二数据,并观察地址总线上指示的地址值。 第一和第二数据分别写入第一和第二寄存器。 第一和第二地址检测单元分别接收由总线接口观察到的地址值。 当第一地址检测单元检测到与第一数据的值对应的地址值时,输出第一检测信号。 当第二地址检测单元检测到具有与第二数据的值对应的第一数据的增量的地址值时,输出第二检测信号。 在从开始输出第一检测信号到输出第二检测信号的结束期间,给予总线利用权的控制单元提高一个总线主机的优先级。
    • 15. 发明授权
    • Asynchronous serial data receiver for packet transfer
    • 用于数据包传输的异步串行数据接收器
    • US07313202B2
    • 2007-12-25
    • US10656252
    • 2003-09-08
    • Yutaka Kawashima
    • Yutaka Kawashima
    • H04L27/06
    • H04J3/0632
    • A receiver provides a differential signal of first and second signals as received serial data. A tracking circuit receives the received serial data and a clock signal to generate a synchronous clock signal based on the clock signal by tracking the received serial data. Then the tracking circuit generates a synchronous serial data synchronized with the synchronous clock signal. An idle detector receives the first signal and the second signal. Then the idle detector detects an idle period of the first and second signals to provide an idle signal. A memory stores the serial data in response to transitions in the synchronous clock signal. The memory provides the stored data in response to transitions in the clock signal. The memory stops storing based on a hold signal. A data protector generates the hold signal to provide the hold signal for the memory.
    • 接收机提供作为接收串行数据的第一和第二信号的差分信号。 跟踪电路通过跟踪所接收的串行数据,接收所接收的串行数据和时钟信号,以通过时钟信号产生同步时钟信号。 然后跟踪电路产生与同步时钟信号同步的同步串行数据。 空闲检测器接收第一信号和第二信号。 然后,空闲检测器检测第一和第二信号的空闲周期以提供空闲信号。 存储器存储响应于同步时钟信号中的转换的串行数据。 存储器响应时钟信号中的转换提供存储的数据。 存储器基于保持信号停止存储。 数据保护器产生保持信号以提供存储器的保持信号。