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11. 发明授权

US06683002B1 Method to create a copper diffusion deterrent interface 失效
公开(公告)号：US06683002B1
公开(公告)日：2004-01-27
申请号：US09636580
申请日：2000-08-10
申请人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
发明人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/28556 , H01L21/31111 , H01L21/314 , H01L21/76807
摘要： Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

12. 发明授权

US06417088B1 Method of application of displacement reaction to form a conductive cap layer for flip-chip, COB, and micro metal bonding 有权
标题翻译：应用位移反应形成倒装芯片，COB和微金属接合的导电盖层的方法
公开(公告)号：US06417088B1
公开(公告)日：2002-07-09
申请号：US09624019
申请日：2000-07-24
申请人： Kwok Keung Paul Ho , Yi Xu , Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
发明人： Kwok Keung Paul Ho , Yi Xu , Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
IPC分类号： H01L2144
CPC分类号： H01L24/48 , H01L21/288 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05147 , H01L2224/05644 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/48644 , H01L2224/48699 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2224/48744
摘要： A method of forming a conductive cap layer over a metal bonding pad comprises the following steps. A semiconductor structure is provided having an exposed, recessed metal bonding pad within a layer opening. The layer has an upper surface. The exposed metal bonding pad is treated with a solution containing soluble metal ions to form a conductive cap over the metal bonding pad. The conductive cap layer is comprised of the solution metal and has a predetermined thickness. An external bonding element may then be bonded to the conductive cap, forming an electrical connection with the metal bonding pad.
摘要翻译：在金属焊盘上形成导电盖层的方法包括以下步骤。提供了一种半导体结构，其在层开口内具有暴露的凹陷的金属接合焊盘。该层具有上表面。暴露的金属焊盘用含有可溶性金属离子的溶液处理，以在金属焊盘上形成导电盖。导电盖层由溶液金属构成并具有预定的厚度。然后可以将外部接合元件接合到导电盖，与金属接合焊盘形成电连接。

13. 发明授权

US06391783B1 Method to thin down copper barriers in deep submicron geometries by using alkaline earth element, barrier additives, or self assembly technique 有权
标题翻译：通过使用碱土元素，阻隔添加剂或自组装技术在深亚微米几何图形中减薄铜屏障的方法
公开(公告)号：US06391783B1
公开(公告)日：2002-05-21
申请号：US09615811
申请日：2000-07-13
申请人： John Sudijono , Yakub Aliyu , Mei Sheng Zhou , Simon Chooi , Subhash Gupta , Sudipto Roy , Paul Ho , Yi Xu
发明人： John Sudijono , Yakub Aliyu , Mei Sheng Zhou , Simon Chooi , Subhash Gupta , Sudipto Roy , Paul Ho , Yi Xu
IPC分类号： H01L2131
CPC分类号： H01L21/76844 , H01L21/288 , H01L21/76867
摘要： A method of forming a metal plug, comprising the following steps. An etched dielectric layer, over a conductive layer, over a semiconductor structure are provided. The etched dielectric layer having a via hole and an exposed periphery. The etched dielectric layer is treated with at least one alkaline earth element source to form an in-situ metal barrier layer within the dielectric layer exposed periphery. A metal plug is formed within the via hole wherein the in-situ metal barrier layer prevents diffusion of the metal from the metal plug into the dielectric oxide layer.
摘要翻译：一种形成金属塞的方法，包括以下步骤。提供了在半导体结构之上的导电层上的蚀刻介电层。蚀刻的介电层具有通孔和暴露的周边。蚀刻的电介质层用至少一个碱土元素源处理，以在电介质层外露的外围形成原位金属阻挡层。在通孔内形成金属塞，其中原位金属阻挡层防止金属从金属塞扩散到电介质氧化物层中。

14. 发明授权

US06378759B1 Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding 有权
标题翻译：导电盖层在倒装芯片，COB和微金属接合中的应用方法
公开(公告)号：US06378759B1
公开(公告)日：2002-04-30
申请号：US09618261
申请日：2000-07-18
申请人： Kwok Keung Paul Ho , Simon Chooi , Yi Xu , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
发明人： Kwok Keung Paul Ho , Simon Chooi , Yi Xu , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
IPC分类号： B23K3102
CPC分类号： H01L24/85 , B23K20/007 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/05187 , H01L2224/05624 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/85 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/04953 , H01L2224/78 , H01L2924/00
摘要： A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.
摘要翻译：将接合元件接合到金属接合焊盘的方法包括以下步骤。提供了一种在层开口内具有暴露的凹陷金属接合焊盘的半导体结构。该层具有上表面。在金属焊盘上形成具有预定厚度的导电盖。接合元件结合到导电盖以与金属接合焊盘形成电连接。

15. 发明授权

US06352921B1 Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization 有权
公开(公告)号：US06352921B1
公开(公告)日：2002-03-05
申请号：US09619377
申请日：2000-07-19
申请人： Licheng M. Han , Yi Xu , Joseph Zhifeng Xie , Mei Sheng Zhou , Simon Chooi
发明人： Licheng M. Han , Yi Xu , Joseph Zhifeng Xie , Mei Sheng Zhou , Simon Chooi
IPC分类号： H01L214763
CPC分类号： H01L21/76834 , H01L21/76807 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.

16. 发明授权

US06350689B1 Method to remove copper contamination by using downstream oxygen and chelating agent plasma 失效
标题翻译：使用下游氧和螯合剂等离子体去除铜污染的方法
公开(公告)号：US06350689B1
公开(公告)日：2002-02-26
申请号：US09839962
申请日：2001-04-23
申请人： Paul Ho , Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Yi Xu
发明人： Paul Ho , Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Yi Xu
IPC分类号： H01L2144
CPC分类号： H01L21/02074 , H01L21/02046 , H01L21/0209 , H01L21/32136 , Y10S438/906
摘要： A method of removing copper contamination from a semiconductor wafer, comprising the following steps. A semiconductor wafer having copper contamination thereon is provided. An oxidizing radical containing downstream plasma is provided from a first source (alternatively halogen (F2, Cl2, or Br2) may be used as on oxidizing agent). A vaporized chelating agent is provided from a second source. The oxidizing radical containing downstream plasma and vaporized chelating agent are mixed to form an oxidizing radical containing downstream plasma/vaporized chelating agent mixture. The mixture is directed to the copper contamination so that the mixture reacts with the copper contamination to form a volatile product. The volatile product is removed from the proximity of the wafer.
摘要翻译：一种从半导体晶片去除铜污染的方法，包括以下步骤。提供其上具有铜污染的半导体晶片。从第一来源提供含有下游等离子体的氧化基团（或者可以在氧化剂上使用卤素（F2，Cl2或Br2））。从第二来源提供蒸发的螯合剂。将含有下游等离子体和气化螯合剂的氧化基团混合以形成含有下游等离子体/汽化螯合剂混合物的氧化基团。混合物被引导到铜污染物，使得混合物与铜污染物反应形成挥发性产物。从晶片附近去除挥发性产物。

17. 发明授权

US06331479B1 Method to prevent degradation of low dielectric constant material in copper damascene interconnects 有权
标题翻译：防止铜大马士革互连中低介电常数材料退化的方法
公开(公告)号：US06331479B1
公开(公告)日：2001-12-18
申请号：US09398294
申请日：1999-09-20
申请人： Jianxun Li , Mei Sheng Zhou , Yi Xu , Simon Chooi
发明人： Jianxun Li , Mei Sheng Zhou , Yi Xu , Simon Chooi
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/31144 , H01L21/7681 , H01L21/76811 , H01L21/76835
摘要： A method of fabricating trenches has been achieved. The method may be applied to damascene and dual damascene contacts to prevent damage to organic low dielectric constant materials due to photoresist ashing. A semiconductor substrate is provided. A first dielectric layer is deposited overlying the semiconductor substrate. A first etch stopping layer is deposited overlying the first dielectric layer. A second etch stopping layer is deposited overlying the first etch stopping layer. An optional anti-reflective coating is applied. A photoresist layer is deposited. The photoresist layer is patterned to define openings for planned trenches. The second etch stopping layer is etched through to form a hard mask for the planned trenches. The photoresist layer is stripped away by ashing where the first etch stopping layer protects the first dielectric layer from damage due to the presence of oxygen radicals. The first etch stopping layer is etched through to complete the trenches, and the integrated circuit device is completed.
摘要翻译：已经实现了制造沟槽的方法。该方法可以应用于镶嵌和双镶嵌接触，以防止由于光致抗蚀剂灰化而损坏有机低介电常数材料。提供半导体衬底。沉积在半导体衬底上的第一介电层。第一蚀刻停止层沉积在第一介电层上。第二蚀刻停止层沉积在第一蚀刻停止层上。应用可选的抗反射涂层。沉积光致抗蚀剂层。图案化光致抗蚀剂层以限定计划沟槽的开口。蚀刻第二蚀刻停止层以形成用于所计划的沟槽的硬掩模。光致抗蚀剂层通过灰化被剥离，其中第一蚀刻停止层保护第一介电层免受由于氧自由基的存在的损害。蚀刻第一蚀刻停止层以完成沟槽，并且完成集成电路器件。

18. 发明授权

US06207554B1 Gap filling process in integrated circuits using low dielectric constant materials 有权
标题翻译：使用低介电常数材料的集成电路中的间隙填充过程
公开(公告)号：US06207554B1
公开(公告)日：2001-03-27
申请号：US09351237
申请日：1999-07-12
申请人： Yi Xu , Jia Zhen Zheng , Jane C. M. Hui , Charles Lin , Yih Shung Lin
发明人： Yi Xu , Jia Zhen Zheng , Jane C. M. Hui , Charles Lin , Yih Shung Lin
IPC分类号： H01L214763
CPC分类号： H01L21/02164 , H01L21/02282 , H01L21/02337 , H01L21/0332 , H01L21/31053 , H01L21/31058 , H01L21/31144 , H01L21/312 , H01L21/3185 , H01L21/32139 , H01L21/76819 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76837
摘要： It is the general object of the present invention to provide an improved method of fabricating semiconductor integrated circuit devices, specifically by describing an improved process of fabricating multilevel metal structures using low dielectric constant materials. The present invention relates to an improved processing methods for stable and planar intermetal dielectrics, with low dielectric constants. The first embodiment uses a stabilizing adhesion layer between the bottom, low dielectric constant layer and the top dielectric layer. The advantages are: (i) improved adhesion and stability of the low dielectric layer and the top dielectric oxide (ii) over all layer thickness of the dielectric layers can be reduced, hence lowering the parasitic capacitance of these layers. In the second embodiment, the method uses a multi-layered “hard mask” on metal interconnect lines with a silicon oxynitride DARC, dielectric anti-reflective coating on top of metal. A double coating scheme of low dielectric constant insulators are used in this application. The third embodiment uses a hard mask stack over the interconnect metal lines, with a silicon oxynitride DARC costing on top of metal, and an adhesion layer between the low dielectric material and the top dielectric layer.
摘要翻译：本发明的总体目的是提供一种制造半导体集成电路器件的改进方法，特别是通过描述使用低介电常数材料制造多层金属结构的改进方法。本发明涉及一种具有低介电常数的稳定和平坦的金属间电介质的改进的处理方法。第一实施例使用底部，低介电常数层和顶部介电层之间的稳定粘合层。优点是：（i）可以降低介电层的所有层厚度上的低介电层和顶部电介质氧化物（ii）的粘附性和稳定性，因此降低这些层的寄生电容。在第二实施例中，该方法在具有氮氧化硅DARC的金属互连线上使用多层“硬掩模”，金属顶部具有介电抗反射涂层。本申请中使用低介电常数绝缘体的双重涂层方案。第三实施例在互连金属线上使用硬掩模叠层，在金属顶部成本计算氮氧化硅DARC，以及低电介质材料和顶部电介质层之间的粘合层。

19. 外观设计

USD1013759S1 Camera lens 有权
公开(公告)号：USD1013759S1
公开(公告)日：2024-02-06
申请号：US29761536
申请日：2020-12-09
申请人： Yi Xu , Zhiquan Yang , Yonghui Yuan , Jieming Li , Sufan Peng
设计人： Yi Xu , Zhiquan Yang , Yonghui Yuan , Jieming Li , Sufan Peng
摘要： FIG. 1 is a perspective view of a camera lens showing our new design;
FIG. 2 is a front elevation view thereof;
FIG. 3 is a rear elevation view thereof;
FIG. 4 is a left side elevation view thereof;
FIG. 5 is a right side elevation view thereof;
FIG. 6 is a top plan view thereof;
FIG. 7 is a bottom plan view thereof; and,
FIG. 8 is an enlarged portion view taken from encircled portion labeled, “FIG. 8,” in FIG. 2.
The dashed-dot lines illustrate the boundary of the enlarged portion view of FIG. 8 shown in FIGS. 2 and 8 and form no part of the claimed design. The even dashed broken lines in the figures show portions of the camera lens which form no part of the claimed design.

20. 发明授权

US10809603B1 LCD projector 有权
公开(公告)号：US10809603B1
公开(公告)日：2020-10-20
申请号：US16563827
申请日：2019-09-07
申请人： Yi Xu
发明人： Yi Xu
IPC分类号： G03B21/00 , G03B21/16 , G03B21/20 , G03B21/14 , G03B33/08 , H04N9/31
摘要： The invention discloses a novel LCD projector, comprising an imaging system with single-light path system for LCD projector time-division display, a lighting system with PCS (P light converted into S light) function, a three-primary-colors LED light source with microlenses, and a heat dissipation system with dust-proof and self-cleaning function; the monochrome LCD screen of the imaging system has a high light transmittance and resolution, achieving higher brightness and resolution; the lighting part has a polarized light conversion function, which converts the useless P light into useful S light, improving the light utilization and increasing the brightness; a transparent antifouling coating is applied on the optical components of the heat dissipation system to reduce dust adsorption; ultrasonic vibrators are mounted on the optical components to shake off the dust attached; the light source uses the microlens to converge the three-primary-color LED light source to improve light efficiency and uniformity.

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