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    • 1. 发明授权
    • Gap filling process in integrated circuits using low dielectric constant materials
    • 使用低介电常数材料的集成电路中的间隙填充过程
    • US06207554B1
    • 2001-03-27
    • US09351237
    • 1999-07-12
    • Yi XuJia Zhen ZhengJane C. M. HuiCharles LinYih Shung Lin
    • Yi XuJia Zhen ZhengJane C. M. HuiCharles LinYih Shung Lin
    • H01L214763
    • H01L21/02164H01L21/02282H01L21/02337H01L21/0332H01L21/31053H01L21/31058H01L21/31144H01L21/312H01L21/3185H01L21/32139H01L21/76819H01L21/76829H01L21/76832H01L21/76834H01L21/76837
    • It is the general object of the present invention to provide an improved method of fabricating semiconductor integrated circuit devices, specifically by describing an improved process of fabricating multilevel metal structures using low dielectric constant materials. The present invention relates to an improved processing methods for stable and planar intermetal dielectrics, with low dielectric constants. The first embodiment uses a stabilizing adhesion layer between the bottom, low dielectric constant layer and the top dielectric layer. The advantages are: (i) improved adhesion and stability of the low dielectric layer and the top dielectric oxide (ii) over all layer thickness of the dielectric layers can be reduced, hence lowering the parasitic capacitance of these layers. In the second embodiment, the method uses a multi-layered “hard mask” on metal interconnect lines with a silicon oxynitride DARC, dielectric anti-reflective coating on top of metal. A double coating scheme of low dielectric constant insulators are used in this application. The third embodiment uses a hard mask stack over the interconnect metal lines, with a silicon oxynitride DARC costing on top of metal, and an adhesion layer between the low dielectric material and the top dielectric layer.
    • 本发明的总体目的是提供一种制造半导体集成电路器件的改进方法,特别是通过描述使用低介电常数材料制造多层金属结构的改进方法。 本发明涉及一种具有低介电常数的稳定和平坦的金属间电介质的改进的处理方法。 第一实施例使用底部,低介电常数层和顶部介电层之间的稳定粘合层。 优点是:(i)可以降低介电层的所有层厚度上的低介电层和顶部电介质氧化物(ii)的粘附性和稳定性,因此降低这些层的寄生电容。 在第二实施例中,该方法在具有氮氧化硅DARC的金属互连线上使用多层“硬掩模”,金属顶部具有介电抗反射涂层。 本申请中使用低介电常数绝缘体的双重涂层方案。 第三实施例在互连金属线上使用硬掩模叠层,在金属顶部成本计算氮氧化硅DARC,以及低电介质材料和顶部电介质层之间的粘合层。
    • 2. 发明授权
    • Method for reducing microloading in an etchback of spin-on-glass or
polymer
    • 减少旋涂玻璃或聚合物回蚀时的微载荷的方法
    • US5930677A
    • 1999-07-27
    • US845252
    • 1997-04-21
    • Jia Zhen ZhengGuo Li Qi MikeYi Xu
    • Jia Zhen ZhengGuo Li Qi MikeYi Xu
    • H01L21/3105H01L21/314H01L21/316H01L21/768
    • H01L21/02164H01L21/02126H01L21/022H01L21/02274H01L21/02282H01L21/31055H01L21/316H01L21/31612H01L21/76819
    • A method for forming a planarized interlevel dielectric layer without degradation due to the microloading effect from spin-on material etchback is described. A patterned first conducting layer is provided over an insulating layer on a semiconductor substrate. An improved interlevel dielectric layer is formed overlying the patterned first conducting layer by the following steps. A first oxide layer is deposited overlying the patterned first conducting layer and the insulating layer. A spin-on material layer is coated overlying the first oxide layer and etched back using O.sub.2 gas added to the CHF.sub.3 /CF.sub.4 chemistry until the first oxide layer is exposed overlying the patterned first conducting layer wherein microloading effects from the etching back of the spin-on material layer are lower than microloading effects in a conventional interlevel dielectric layer. A second oxide layer is deposited to complete the interlevel dielectric layer. A second conducting layer is deposited over the interlevel dielectric layer and patterned to complete the fabrication of the integrated circuit device.
    • 描述了由于旋涂材料回蚀引起的微加载效应而形成平坦化层间电介质层而不降解的方法。 图案化的第一导电层设置在半导体衬底上的绝缘层上。 通过以下步骤形成覆盖图案化的第一导电层的改进的层间介电层。 沉积在图案化的第一导电层和绝缘层上的第一氧化物层。 将旋涂材料层涂覆在第一氧化物层上,并使用添加到CHF 3 / CF 4化学物质的O 2气体进行回蚀,直到第一氧化物层暴露在图案化的第一导电层上,其中来自旋转 - 材料层在常规层间介质层中低于微载荷效应。 沉积第二氧化物层以完成层间电介质层。 第二导电层沉积在层间电介质层上并被图案化以完成集成电路器件的制造。