专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20080217775A1 Method of forming contact plugs for eliminating tungsten seam issue 审中-公开
标题翻译：形成用于消除钨焊缝问题的接触塞的方法
公开(公告)号：US20080217775A1
公开(公告)日：2008-09-11
申请号：US11714770
申请日：2007-03-07
申请人： Chih-Yang Pai , Wen-Chuan Chiang , Chung-Yi Yu , Yeur-Luen Tu , Yuan-Hung Liu , Hsiang-Fan Lee , Chuan-Jong Wang
发明人： Chih-Yang Pai , Wen-Chuan Chiang , Chung-Yi Yu , Yeur-Luen Tu , Yuan-Hung Liu , Hsiang-Fan Lee , Chuan-Jong Wang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76877 , H01L21/76849 , H01L27/10855 , H01L27/10888
摘要： A method of forming a contact plug of an eDRAM device includes the following steps: forming a tungsten layer with tungsten seam on a dielectric layer to fill a contact hole; removing the tungsten layer from the top surface of the dielectric layer, recessing the tungsten layer in the contact hole to form a recess of about 600˜900 Angstroms in depth below the top surface of the dielectric layer, depositing a conductive layer on the dielectric layer and the recessed tungsten plug to fill the recess; and removing the conductive layer from the top surface of the dielectric layer to form a conductive plug on the recessed tungsten plug in the contact hole.
摘要翻译：形成eDRAM器件的接触插塞的方法包括以下步骤：在电介质层上形成具有钨接缝的钨层以填充接触孔; 从电介质层的顶表面去除钨层，使接触孔中的钨层凹陷，以在电介质层的顶表面下方深度形成约600〜900埃的凹陷，在电介质层上沉积导电层和凹入的钨塞填充凹槽; 并且从电介质层的顶表面去除导电层，以在接触孔中的凹入的钨插塞上形成导电插塞。

12. 发明授权

US07214589B2 Flash memory cell and methods for fabricating same 有权
标题翻译：闪存单元及其制造方法
公开(公告)号：US07214589B2
公开(公告)日：2007-05-08
申请号：US10803448
申请日：2004-03-18
申请人： Yuan-Hung Liu , Yeur-Luen Tu
发明人： Yuan-Hung Liu , Yeur-Luen Tu
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A split gate flash memory cell having floating gates with sharp, upwardly flared corners, protective caps of dielectric material which are substantially square or rectangular in cross-section, and elongated and thin Vss dielectric spacers disposed along substantially planar side walls defined by the floating gates and the protective caps.
摘要翻译：具有浮动栅极的分裂栅极闪存单元，其具有尖锐的向上扩展的角，具有基本上为矩形或矩形横截面的介电材料的保护盖，以及沿着由浮动栅极限定的基本平坦的侧壁设置的细长且薄的Vss电介质间隔件和保护盖。

13. 发明申请

US20060183318A1 MAGNETIC MEMORY CELLS AND MANUFACTURING METHODS 有权
标题翻译：磁记忆细胞和制造方法
公开(公告)号：US20060183318A1
公开(公告)日：2006-08-17
申请号：US10906357
申请日：2005-02-15
申请人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
IPC分类号： H01L21/4763 , H01L21/00
CPC分类号： H01L43/12 , H01L27/228
摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.
摘要翻译：改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。然后可以在掩模层和导电通孔上形成导电存储器线。

14. 发明授权

US06352919B1 Method of fabricating a borderless via 有权
标题翻译：制造无边界通孔的方法
公开(公告)号：US06352919B1
公开(公告)日：2002-03-05
申请号：US09620033
申请日：2000-07-20
申请人： Yeur-Luen Tu , Bor-Wen Chan , Yuan-Hung Liu
发明人： Yeur-Luen Tu , Bor-Wen Chan , Yuan-Hung Liu
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/76801
摘要： A method of fabricating a borderless via is disclosed. A semiconductor substrate having a first dielectric layer thereon is provided. Next, a first conductive structure and a second conductive structure whose area is much smaller than said first conductive structure are formed on said first dielectric layer. After that, a second dielectric layer with an uneven surface is formed. Then, a planarizing layer is coated over said second dielectric layer to fill said uneven surface. Next, an etch back process is used to create a etching stop layer consisting of a portion of second dielectric layer. Subsequently, a third dielectric layer is formed over said second dielectric layer followed by selectively etching said third dielectric layer until said second dielectric layer is exposed to create a borderless via.
摘要翻译：公开了制造无边界通孔的方法。提供其上具有第一介电层的半导体衬底。接下来，在所述第一介电层上形成面积比所述第一导电结构小得多的第一导电结构和第二导电结构。之后，形成具有不平坦表面的第二电介质层。然后，在所述第二电介质层上涂覆平坦化层以填充所述不平坦表面。接下来，使用回蚀工艺来产生由第二介电层的一部分组成的蚀刻停止层。随后，在所述第二电介质层上形成第三电介质层，随后选择性地蚀刻所述第三电介质层，直到所述第二电介质层暴露以形成无边界通孔。

15. 发明申请

US20080318378A1 MIM Capacitors with Improved Reliability 有权
标题翻译： MIM电容器具有改进的可靠性
公开(公告)号：US20080318378A1
公开(公告)日：2008-12-25
申请号：US11765971
申请日：2007-06-20
申请人： Chih-Ta Wu , Jason Lee , Chung Chien Wang , Hsing-Lien Lin , Yu-Jen Wang , Yeur-Luen Tu , Chern-Yow Hsu , Yuan-Hung Liu , Chi-Hsin Lo , Chia-Shiung Tsai , Lucy Chang , Chia-Lin Chen , Ming-Chih Tsai
发明人： Chih-Ta Wu , Jason Lee , Chung Chien Wang , Hsing-Lien Lin , Yu-Jen Wang , Yeur-Luen Tu , Chern-Yow Hsu , Yuan-Hung Liu , Chi-Hsin Lo , Chia-Shiung Tsai , Lucy Chang , Chia-Lin Chen , Ming-Chih Tsai
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L27/10814 , H01L27/10852 , H01L28/40 , H01L28/75
摘要： A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.
摘要翻译：提供电容器及其形成方法。该方法包括形成底部电极; 在含氧环境中处理底部电极以将底部电极的顶层转化为缓冲层; 在缓冲层上形成绝缘层; 并在所述绝缘层上形成顶部电极。

16. 发明申请

US20080124912A1 SEMICONDUCTOR METHODS 审中-公开
标题翻译：半导体方法
公开(公告)号：US20080124912A1
公开(公告)日：2008-05-29
申请号：US11461673
申请日：2006-08-01
申请人： Yuan-Hung Liu , Ming Chyi Liu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Ming Chyi Liu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/4763
CPC分类号： H01L21/02274 , H01L21/02115 , H01L21/3086 , H01L21/31116 , H01L21/31144 , H01L21/3146 , H01L21/76816 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L27/115 , H01L27/11521 , H01L27/14632 , H01L27/14687 , H01L28/91 , H01L29/40114 , H01L29/42328 , H01L29/7881
摘要： A method includes the steps of: (a) forming a conductive layer within a dielectric layer formed over a substrate; (b) forming a material layer over the conductive layer and the dielectric layer; (c) forming an opening within the material layer by an etch process to expose a portion of the dielectric layer and a top surface of the conductive layer; (d) forming a first metal-containing layer within the opening substantially covering sidewalls of the material layer and the exposed portion of the second dielectric layer; and (e) removing the material layer by an oxygen-containing plasma process to expose a portion of outer sidewalls of the first metal-containing layer.
摘要翻译：一种方法包括以下步骤：（a）在形成在衬底上的电介质层内形成导电层; （b）在导电层和电介质层上形成材料层; （c）通过蚀刻工艺在所述材料层内形成开口以暴露所述电介质层的一部分和所述导电层的顶表面; （d）在所述开口内形成基本上覆盖所述材料层的侧壁和所述第二介电层的暴露部分的第一含金属层; 和（e）通过含氧等离子体方法去除所述材料层以暴露所述第一含金属层的外侧壁的一部分。

17. 发明授权

US07172908B2 Magnetic memory cells and manufacturing methods 有权
公开(公告)号：US07172908B2
公开(公告)日：2007-02-06
申请号：US10906357
申请日：2005-02-15
申请人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/228
摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

18. 发明授权

US07122424B2 Method for making improved bottom electrodes for metal-insulator-metal crown capacitors 有权
标题翻译：用于金属绝缘体金属冠电容器的改进的底部电极的方法
公开(公告)号：US07122424B2
公开(公告)日：2006-10-17
申请号：US10788175
申请日：2004-02-26
申请人： Yeur-Luen Tu , Yuan-Hung Liu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Yeur-Luen Tu , Yuan-Hung Liu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/8242
CPC分类号： H01L21/32139 , H01L27/10852 , H01L28/91
摘要： A method for making crown-shaped capacitors with uniform capacitance from the center to the edge of the DRAM device is achieved. The uniform capacitance is achieved using a two-step planarization process or a uniformly deposited CVD sacrificial layer. After forming a first conducting layer in openings in an insulator, a sacrificial layer is spin coated on the substrate. The non-uniformity, by virtue of the spin coating, is then partially polished back to form a globally uniform surface followed by a plasma etch-back to leave portions of the sacrificial layer of equal height in the openings. The first conducting layer in the openings is uniformly recessed for making capacitors having uniform values across the DRAM device. In a second approach a relatively thin uniform CVD polymer is deposited requiring only a single polishing step or etch-back to achieve uniform portions of the polymer in the openings.
摘要翻译：实现了从DRAM器件的中心到边缘具有均匀电容的冠形电容器的方法。使用两步平坦化工艺或均匀沉积的CVD牺牲层来实现均匀电容。在绝缘体的开口中形成第一导电层之后，将牺牲层旋涂在基板上。然后通过旋转涂层的不均匀性被部分地抛光以形成全局均匀的表面，随后进行等离子体回蚀，以使开口中具有相等高度的牺牲层的部分留下。开口中的第一导电层均匀地凹进，用于制造跨越DRAM器件的具有均匀值的电容器。在第二种方法中，沉积相对薄的均匀的CVD聚合物，其仅需要单个抛光步骤或蚀刻以在开口中实现聚合物的均匀部分。

19. 发明申请

US20050205922A1 Flash memory cell and methods for fabricating same 有权
标题翻译：闪存单元及其制造方法
公开(公告)号：US20050205922A1
公开(公告)日：2005-09-22
申请号：US10803448
申请日：2004-03-18
申请人： Yuan-Hung Liu , Yeur-Luen Tu
发明人： Yuan-Hung Liu , Yeur-Luen Tu
IPC分类号： H01L21/8238 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A split gate flash memory cell having floating gates with sharp, upwardly flared corners, protective caps of dielectric material which are substantially square or rectangular in cross-section, and elongated and thin Vss dielectric spacers disposed along substantially planar side walls defined by the floating gates and the protective caps.
摘要翻译：具有浮动栅极的分裂栅极闪存单元，其具有尖锐的向上扩展的角，具有基本上为矩形或矩形横截面的介电材料的保护盖，以及沿着由浮动栅极限定的基本平坦的侧壁设置的细长且薄的Vss电介质间隔件和保护盖。

20. 发明申请

US20050191820A1 Method for making improved bottom electrodes for metal-insulator-metal crown capacitors 有权
标题翻译：用于金属绝缘体金属冠电容器的改进的底部电极的方法
公开(公告)号：US20050191820A1
公开(公告)日：2005-09-01
申请号：US10788175
申请日：2004-02-26
申请人： Yeur-Luen Tu , Yuan-Hung Liu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Yeur-Luen Tu , Yuan-Hung Liu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/02 , H01L21/20 , H01L21/3213 , H01L21/8242
CPC分类号： H01L21/32139 , H01L27/10852 , H01L28/91
摘要： A method for making crown-shaped capacitors with uniform capacitance from the center to the edge of the DRAM device is achieved. The uniform capacitance is achieved using a two-step planarization process or a uniformly deposited CVD sacrificial layer. After forming a first conducting layer in openings in an insulator, a sacrificial layer is spin coated on the substrate. The non-uniformity, by virtue of the spin coating, is then partially polished back to form a globally uniform surface followed by a plasma etch-back to leave portions of the sacrificial layer of equal height in the openings. The first conducting layer in the openings is uniformly recessed for making capacitors having uniform values across the DRAM device. In a second approach a relatively thin uniform CVD polymer is deposited requiring only a single polishing step or etch-back to achieve uniform portions of the polymer in the openings.
摘要翻译：实现了从DRAM器件的中心到边缘具有均匀电容的冠形电容器的方法。使用两步平坦化工艺或均匀沉积的CVD牺牲层来实现均匀电容。在绝缘体的开口中形成第一导电层之后，将牺牲层旋涂在基板上。然后通过旋转涂层的不均匀性被部分地抛光以形成全局均匀的表面，随后进行等离子体回蚀，以使开口中具有相等高度的牺牲层的部分留下。开口中的第一导电层均匀地凹进，用于制造跨越DRAM器件的具有均匀值的电容器。在第二种方法中，沉积相对薄的均匀的CVD聚合物，其仅需要单个抛光步骤或蚀刻以在开口中实现聚合物的均匀部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式