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    • 3. 发明授权
    • Methods of fabricating a word-line spacer for wide over-etching window on outside diameter (OD) and strong fence
    • 在外径(OD)和强栅栏上制作用于宽过度蚀刻窗口的字线间隔件的方法
    • US06869837B1
    • 2005-03-22
    • US10758316
    • 2004-01-15
    • Yuan-Hung LiuYeur-Luen TuChin-Ta WuTsung-Hsun HuangHsiu OuyangChi-Hsin LoChia-Shiung Tsai
    • Yuan-Hung LiuYeur-Luen TuChin-Ta WuTsung-Hsun HuangHsiu OuyangChi-Hsin LoChia-Shiung Tsai
    • H01L21/8238H01L21/8247H01L27/115H01L29/76
    • H01L27/11521H01L27/115
    • A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed over the substrate and the inchoate split-gate flash memory structure. The conductive layer having: a upper portion and lower vertical portions over the inchoate split-gate flash memory structure; and lower horizontal portions over the substrate. A dual-thickness oxide layer is formed over the conductive layer and has a greater thickness over the upper portion of the conductive layer. The oxide layer is partially etched back to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer. Then etching: away the exposed portions of the conductive layer over the substrate; and through at least a portion of the thinned oxide layer and into the exposed underlying portion of the conductive layer to expose a portion of the inchoate split-gate flash memory structure and to form the word-line spacers adjacent the inchoate split-gate flash memory structure.
    • 一种制造字线间隔物的方法,包括以下步骤。 提供了具有形成在其上的初始分离栅闪存结构的衬底。 导电层形成在衬底和初生分裂栅极闪存结构之上。 所述导电层具有:上部分裂栅极闪存结构上方的上部和下部垂直部分; 并且在基底上下方水平部分。 在导电层之上形成双层氧化物层,并且在导电层的上部上具有更大的厚度。 将氧化层部分地回蚀刻以从导电层的下部水平部分上方至少去除氧化物层,以暴露导电层的下面部分。 然后蚀刻:将导电层的暴露部分远离衬底; 并且通过至少一部分减薄的氧化物层并进入导电层的暴露的下面的部分,以暴露初步分离栅闪存结构的一部分并且形成邻近先驱分离栅闪存的字线间隔物 结构体。
    • 5. 发明授权
    • Spacer for a split gate flash memory cell and a memory cell employing the same
    • 分离栅闪存单元的间隔器和采用其的存储单元
    • US07202130B2
    • 2007-04-10
    • US10775290
    • 2004-02-10
    • Yuan-Hung LiuChih-Ta WuYeur-Luen TuChi-Hsin LoChia-Shiung Tsai
    • Yuan-Hung LiuChih-Ta WuYeur-Luen TuChi-Hsin LoChia-Shiung Tsai
    • H01L21/336H01L29/788
    • H01L27/11568H01L27/115H01L27/11521H01L29/42324
    • A spacer, a split gate flash memory cell, and related method of forming the same. In one aspect, a composite spacer includes a first spacer insulating layer having a first deposition distribution that varies as a function of a location on a substrate. The composite spacer also includes a second spacer insulating layer having a second deposition distribution that varies in substantial opposition to the first deposition distribution. In another aspect, a composite spacer includes a first spacer insulating layer having a substantially uniform deposition distribution across a surface thereof. The composite spacer also includes a second spacer insulating layer having a varying deposition distribution with a thinner composition in selected regions of the memory cell. In another aspect, a coupling spacer provides for a conductive layer that extends between a floating gate and a substrate insulating layer adjacent a source recessed into the substrate of the memory cell.
    • 间隔物,分裂栅极闪存单元及其相关方法。 在一个方面,一种复合间隔物包括具有第一沉积分布的第一间隔绝缘层,其随着基底上的位置而变化。 复合间隔物还包括具有与第一沉积分布基本相反的第二沉积分布的第二间隔绝缘层。 在另一方面,复合间隔物包括在其表面上具有基本均匀的沉积分布的第一间隔绝缘层。 复合间隔物还包括具有在存储单元的选定区域中具有较薄组成的不同沉积分布的第二间隔绝缘层。 在另一方面,耦合间隔物提供导电层,该导电层在浮置栅极和与凹入到存储器单元的衬底中的源极相邻的衬底绝缘层之间延伸。
    • 9. 发明授权
    • Method for making improved bottom electrodes for metal-insulator-metal crown capacitors
    • 用于金属绝缘体金属冠电容器的改进的底部电极的方法
    • US07122424B2
    • 2006-10-17
    • US10788175
    • 2004-02-26
    • Yeur-Luen TuYuan-Hung LiuChi-Hsin LoChia-Shiung Tsai
    • Yeur-Luen TuYuan-Hung LiuChi-Hsin LoChia-Shiung Tsai
    • H01L21/8242
    • H01L21/32139H01L27/10852H01L28/91
    • A method for making crown-shaped capacitors with uniform capacitance from the center to the edge of the DRAM device is achieved. The uniform capacitance is achieved using a two-step planarization process or a uniformly deposited CVD sacrificial layer. After forming a first conducting layer in openings in an insulator, a sacrificial layer is spin coated on the substrate. The non-uniformity, by virtue of the spin coating, is then partially polished back to form a globally uniform surface followed by a plasma etch-back to leave portions of the sacrificial layer of equal height in the openings. The first conducting layer in the openings is uniformly recessed for making capacitors having uniform values across the DRAM device. In a second approach a relatively thin uniform CVD polymer is deposited requiring only a single polishing step or etch-back to achieve uniform portions of the polymer in the openings.
    • 实现了从DRAM器件的中心到边缘具有均匀电容的冠形电容器的方法。 使用两步平坦化工艺或均匀沉积的CVD牺牲层来实现均匀电容。 在绝缘体的开口中形成第一导电层之后,将牺牲层旋涂在基板上。 然后通过旋转涂层的不均匀性被部分地抛光以形成全局均匀的表面,随后进行等离子体回蚀,以使开口中具有相等高度的牺牲层的部分留下。 开口中的第一导电层均匀地凹进,用于制造跨越DRAM器件的具有均匀值的电容器。 在第二种方法中,沉积相对薄的均匀的CVD聚合物,其仅需要单个抛光步骤或蚀刻以在开口中实现聚合物的均匀部分。
    • 10. 发明申请
    • Method for making improved bottom electrodes for metal-insulator-metal crown capacitors
    • 用于金属绝缘体金属冠电容器的改进的底部电极的方法
    • US20050191820A1
    • 2005-09-01
    • US10788175
    • 2004-02-26
    • Yeur-Luen TuYuan-Hung LiuChi-Hsin LoChia-Shiung Tsai
    • Yeur-Luen TuYuan-Hung LiuChi-Hsin LoChia-Shiung Tsai
    • H01L21/02H01L21/20H01L21/3213H01L21/8242
    • H01L21/32139H01L27/10852H01L28/91
    • A method for making crown-shaped capacitors with uniform capacitance from the center to the edge of the DRAM device is achieved. The uniform capacitance is achieved using a two-step planarization process or a uniformly deposited CVD sacrificial layer. After forming a first conducting layer in openings in an insulator, a sacrificial layer is spin coated on the substrate. The non-uniformity, by virtue of the spin coating, is then partially polished back to form a globally uniform surface followed by a plasma etch-back to leave portions of the sacrificial layer of equal height in the openings. The first conducting layer in the openings is uniformly recessed for making capacitors having uniform values across the DRAM device. In a second approach a relatively thin uniform CVD polymer is deposited requiring only a single polishing step or etch-back to achieve uniform portions of the polymer in the openings.
    • 实现了从DRAM器件的中心到边缘具有均匀电容的冠形电容器的方法。 使用两步平坦化工艺或均匀沉积的CVD牺牲层来实现均匀电容。 在绝缘体的开口中形成第一导电层之后,将牺牲层旋涂在基板上。 然后通过旋转涂层的不均匀性被部分地抛光以形成全局均匀的表面,随后进行等离子体回蚀,以使开口中具有相等高度的牺牲层的部分留下。 开口中的第一导电层均匀地凹进,用于制造跨越DRAM器件的具有均匀值的电容器。 在第二种方法中,沉积相对薄的均匀的CVD聚合物,其仅需要单个抛光步骤或蚀刻以在开口中实现聚合物的均匀部分。