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11. 发明申请

US20080191281A1 STRESSED SOI FET HAVING TENSILE AND COMPRESSIVE DEVICE REGIONS 失效
标题翻译：具有拉伸和压缩设备区域的应力SOI FET
公开(公告)号：US20080191281A1
公开(公告)日：2008-08-14
申请号：US11673716
申请日：2007-02-12
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203 , H01L29/7843
摘要： A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of the active semiconductor region which shares a common boundary with the first portion. After forming trenches in the SOI layer, the SOI substrate is heated with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion. For example, when the first stress is tensile, the second stress is compressive, or the first stress can be compressive when the second stress is tensile. Desirably, the stressed layer is then removed to expose the first and second portions of the active semiconductor region. Desirably, the field effect transistor (“FET”) is formed to include (i) a source region in the first portion, (ii) a drain region in the first portion, and (iii) a channel region in the second portion.
摘要翻译：提供一种用于制造在SOI衬底的绝缘体上半导体（“SOI”）层中具有沟道区的场效应晶体管（“FET”）的方法。理想地，在这种方法中，牺牲应力层形成为覆盖有源半导体区域的第一部分，但不覆盖与第一部分共用公共边界的有源半导体区域的第二部分。在SOI层中形成沟槽之后，将SOI衬底上的应力层充分加热，使得应力层松弛，从而使应力层对第一部分施加第一应力并向第二部分施加第二应力一部分。例如，当第一应力是拉伸时，第二应力是压缩的，或者当第二应力是拉伸时，第一应力可以是压缩的。理想地，应力层被去除以暴露有源半导体区域的第一和第二部分。期望地，场效应晶体管（“FET”）形成为包括（i）第一部分中的源极区域，（ii）第一部分中的漏极区域，以及（iii）第二部分中的沟道区域。

12. 发明授权

US07632724B2 Stressed SOI FET having tensile and compressive device regions 失效
标题翻译：具有拉伸和压缩装置区域的受压SOI FET
公开(公告)号：US07632724B2
公开(公告)日：2009-12-15
申请号：US11673716
申请日：2007-02-12
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L21/00
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203 , H01L29/7843
摘要： A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of the active semiconductor region which shares a common boundary with the first portion. After forming trenches in the SOI layer, the SOI substrate is heated with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion. For example, when the first stress is tensile, the second stress is compressive, or the first stress can be compressive when the second stress is tensile. Desirably, the stressed layer is then removed to expose the first and second portions of the active semiconductor region. Desirably, the field effect transistor (“FET”) is formed to include (i) a source region in the first portion, (ii) a drain region in the first portion, and (iii) a channel region in the second portion.
摘要翻译：提供一种用于制造在SOI衬底的绝缘体上半导体（“SOI”）层中具有沟道区的场效应晶体管（“FET”）的方法。理想地，在这种方法中，牺牲应力层形成为覆盖有源半导体区域的第一部分，但不覆盖与第一部分共用共同边界的有源半导体区域的第二部分。在SOI层中形成沟槽之后，将SOI衬底上的应力层充分加热，使得应力层松弛，从而使应力层对第一部分施加第一应力并向第二部分施加第二应力一部分。例如，当第一应力是拉伸时，第二应力是压缩的，或者当第二应力是拉伸时，第一应力可以是压缩的。理想地，应力层被去除以暴露有源半导体区域的第一和第二部分。期望地，场效应晶体管（“FET”）形成为包括（i）第一部分中的源极区域，（ii）第一部分中的漏极区域，以及（iii）第二部分中的沟道区域。

13. 发明申请

US20080237709A1 AFTER GATE FABRICATION OF FIELD EFFECT TRANSISTOR HAVING TENSILE AND COMPRESSIVE REGIONS 失效
标题翻译：在具有拉伸和压缩区域的场效应晶体管的栅格制造之后
公开(公告)号：US20080237709A1
公开(公告)日：2008-10-02
申请号：US11693786
申请日：2007-03-30
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L29/78 , H01L21/84
CPC分类号： H01L29/66628 , H01L21/84 , H01L29/1083 , H01L29/66772 , H01L29/7842 , H01L29/7843 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： A field effect transistor (“FET”) is formed to include a stress in a channel region of an active semiconductor region of an SOI substrate. A gate is formed to overlie the active semiconductor region, after which a sacrificial stressed layer is formed which overlies the gate and the active semiconductor region. Then, the SOI substrate is heated to cause a flowable dielectric material in a buried dielectric layer of the SOI substrate to soften and reflow. As a result of the reflowing, the sacrificial stressed layer induces stress in a channel region of the active semiconductor region underlying the gate. A source region and a drain region are formed in the active semiconductor region, desirably after removing the sacrificial stressed layer.
摘要翻译：形成场效应晶体管（“FET”）以在SOI衬底的有源半导体区域的沟道区域中包含应力。形成栅极覆盖有源半导体区域，之后形成覆盖在栅极和有源半导体区域上的牺牲应力层。然后，加热SOI衬底，使SOI衬底的埋入介质层中的可流动介电材料软化和回流。作为回流的结果，牺牲应力层在栅极下方的有源半导体区域的沟道区域中引起应力。源极区域和漏极区域形成在有源半导体区域中，理想地在除去牺牲应力层之后。

14. 发明申请

US20080169508A1 STRESSED SOI FET HAVING DOPED GLASS BOX LAYER 有权
标题翻译：具有DOPED GLASS BOX LAYER的应力SOI FET
公开(公告)号：US20080169508A1
公开(公告)日：2008-07-17
申请号：US11622056
申请日：2007-01-11
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/7849
摘要： A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate including (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (ii) a buried oxide (“BOX”) layer, the BOX layer including a layer of doped silicate glass. In such method, a sacrificial stressed layer is deposited to overlie the SOI layer and trenches are etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften, thereby causing the sacrificial stressed layer to apply stress to the SOI layer to form a stressed SOI layer. A dielectric material can then be deposited in the trenches to form isolation regions contacting peripheral edges of the stressed SOI layer, the isolation regions extending from a major surface of the stressed SOI layer towards the BOX layer. The sacrificial stressed layer can then be removed to expose the stressed SOI layer.
摘要翻译：提供了一种用于制造绝缘体上半导体（“SOI”）衬底的方法，其包括（i）通过（ii）掩埋氧化物（“BOX”）层从（ii）体半导体层分离的单晶硅的SOI层 BOX层包括一层掺杂的硅酸盐玻璃。在这种方法中，沉积牺牲应力层以覆盖SOI层，并且通过牺牲应力层蚀刻沟槽并进入SOI层。用牺牲应力层对SOI衬底进行充分加热，使玻璃层软化，从而使牺牲应力层向SOI层施加应力以形成受应力的SOI层。然后可以将电介质材料沉积在沟槽中以形成接触应力SOI层的外围边缘的隔离区域，隔离区域从受应力的SOI层的主表面延伸到BOX层。然后可以去除牺牲应力层以暴露受应力的SOI层。

15. 发明申请

US20080050863A1 SEMICONDUCTOR STRUCTURE INCLUDING MULTIPLE STRESSED LAYERS 审中-公开
标题翻译：半导体结构，包括多个应力层
公开(公告)号：US20080050863A1
公开(公告)日：2008-02-28
申请号：US11467721
申请日：2006-08-28
申请人： William K. Henson , Dureseti Chidambarrao , Yaocheng Liu
发明人： William K. Henson , Dureseti Chidambarrao , Yaocheng Liu
IPC分类号： H01L21/84
CPC分类号： H01L29/045 , H01L21/28097 , H01L29/4975 , H01L29/66545 , H01L29/66772 , H01L29/7843 , H01L29/78654
摘要： A semiconductor structure and methods for fabricating the semiconductor structure include a gate electrode located over a channel region within a semiconductor substrate and a spacer layer adjacent the gate electrode. The spacer layer extends vertically above the gate electrode. The semiconductor structure also includes a first stressed layer having a first stress located over the gate electrode and a second stressed layer having a second stress different than the first stress located over the first stressed layer. At least a portion of the first stressed layer is laterally contained by the spacer layer. At least a portion of the second stressed layer is not laterally contained by the spacer layer.
摘要翻译：半导体结构和制造半导体结构的方法包括位于半导体衬底内的沟道区上方的栅电极和与栅电极相邻的间隔层。间隔层在栅电极上方垂直延伸。半导体结构还包括具有位于栅极上的第一应力的第一应力层和具有不同于位于第一应力层上方的第一应力的第二应力的第二应力层。第一应力层的至少一部分由间隔层横向容纳。第二应力层的至少一部分不被间隔层横向包含。

16. 发明授权

US07888197B2 Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer 有权
标题翻译：使用牺牲应力层形成具有掺杂玻璃盒层的应力SOI FET的方法
公开(公告)号：US07888197B2
公开(公告)日：2011-02-15
申请号：US11622056
申请日：2007-01-11
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L21/8238
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/7849
摘要： A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate. In such method an SOI substrate is formed to include (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (iii) a buried oxide (“BOX”) layer including a layer of doped silicate glass. A sacrificial stressed layer is deposited onto the SOI substrate to overlie the SOI layer. Trenches are then etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften and the sacrificial stressed layer to relax, to thereby apply a stress to the SOI layer to form a stressed SOI layer. The trenches in the stressed SOI layer are then filled with a dielectric material to form trench isolation regions contacting peripheral edges of the stressed SOI layer, the trench isolation regions extending downwardly from a major surface of the stressed SOI layer towards the BOX layer. The sacrificial stressed layer is then removed to expose the stressed SOI layer. Field effect transistors can then be formed in the stressed SOI layer.
摘要翻译：提供了一种用于制造绝缘体上半导体（“SOI”）衬底的方法。在这种方法中，形成SOI衬底，其包括（i）通过（iii）包含掺杂硅酸盐玻璃层的掩埋氧化物（“BOX”）层从（ii）体半导体层分离的单晶硅的SOI层。牺牲应力层沉积在SOI衬底上以覆盖SOI层。然后将沟槽蚀刻穿过牺牲应力层并进入SOI层。用牺牲应力层将SOI衬底充分加热，使玻璃层软化，牺牲应力层松弛，从而向SOI层施加应力以形成受应力的SOI层。然后用电介质材料填充受应力的SOI层中的沟槽，以形成接触应力SOI层的外围边缘的沟槽隔离区，沟槽隔离区域从受应力的SOI层的主表面向BOX层向下延伸。然后去除牺牲应力层以暴露受应力的SOI层。然后可以在受应力的SOI层中形成场效应晶体管。

17. 发明申请

US20080054357A1 SEMICONDUCTOR STRUCTURE WITH ENHANCED PERFORMANCE USING A SIMPLIFIED DUAL STRESS LINER CONFIGURATION 失效
标题翻译：使用简化的双应力衬里配置提高性能的半导体结构
公开(公告)号：US20080054357A1
公开(公告)日：2008-03-06
申请号：US11468958
申请日：2006-08-31
申请人： Dureseti Chidambarrao , Yaocheng Liu , William K. Henson
发明人： Dureseti Chidambarrao , Yaocheng Liu , William K. Henson
IPC分类号： H01L27/12
CPC分类号： H01L21/28097 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/4908 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/7843
摘要： A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has an upper surface that is substantially planar with an upper surface of a fully silicided gate electrode of the nFET. In accordance with the present invention, the first stress liner is not present atop the nFET including the fully silicided gate electrode. Instead, the first stress liner of the present invention partially wraps around, i.e., surrounds the sides of, the nFET with the fully silicided gate electrode. A second stress liner having an opposite polarity as that of the first stress liner (i.e., of an opposite stress type) is located on the upper surface of the first stress liner as well as atop the nFET that contains the fully silicided FET. In accordance with the present invention, the first stress liner is a tensile stress liner and the second stress liner is a compressive stress liner.
摘要翻译：提供了包括具有完全硅化栅电极的nFET的半导体结构，其中使用新的双应力衬垫配置来增强位于栅电极下方的沟道区中的应力。新的双应力衬垫构造包括第一应力衬垫，其具有与nFET的完全硅化栅电极的上表面基本上平面的上表面。根据本发明，第一应力衬垫不存在于包括全硅化物栅电极的nFET顶部。相反，本发明的第一应力衬垫部分地包裹着nFET的侧面，即用完全硅化的栅电极包围nFET。具有与第一应力衬垫相反极性（即相反应力类型）的第二应力衬垫位于第一应力衬垫的上表面上以及位于包含完全硅化FET的nFET顶上。根据本发明，第一应力衬垫是拉伸应力衬垫，第二应力衬垫是压应力衬垫。

18. 发明授权

US07560326B2 Silicon/silcion germaninum/silicon body device with embedded carbon dopant 失效
标题翻译：硅/硅锗/硅体器件与嵌入式碳掺杂剂
公开(公告)号：US07560326B2
公开(公告)日：2009-07-14
申请号：US11381810
申请日：2006-05-05
申请人： Anda C. Mocuta , Dureseti Chidambarrao , Ricardo A. Donaton , David M. Onsongo , Kern Rim
发明人： Anda C. Mocuta , Dureseti Chidambarrao , Ricardo A. Donaton , David M. Onsongo , Kern Rim
IPC分类号： H01L21/8234 , H01L31/0392
CPC分类号： H01L21/823807 , H01L29/1054 , H01L29/66636 , H01L29/78687
摘要： A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.
摘要翻译：一种制造半导体器件的半导体结构和方法，特别是NFET器件。这些装置包括在应力诱导层上提供的应力接收层，其中在其间的界面处的材料减少了结构中失配位错的发生和传播。应力接收层是硅（Si），应力诱导层是硅锗（SiGe），并且材料是在形成器件期间通过掺杂层提供的碳。也可以在整个SiGe层中掺杂碳。

19. 发明授权

US08296691B2 Methodology for improving device performance prediction from effects of active area corner rounding 失效
标题翻译：从活动区域四舍五入的角度提高设备性能预测的方法
公开(公告)号：US08296691B2
公开(公告)日：2012-10-23
申请号：US11971015
申请日：2008-01-08
申请人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
IPC分类号： G06F17/50 , G06F9/45 , G06G7/48
CPC分类号： G06F17/5036
摘要： A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a simulation includes the deltaW adder values to more accurately describe the characteristics of the transistor device being modeled including modeling of lithographic corner rounding effect on transistor device parametrics.
摘要翻译：一种用于建模半导体晶体管器件结构的系统和方法，所述半导体晶体管器件结构具有设计长度的导线特征，所述导线特征与待建模的电路中的晶体管器件的栅极连接，所述晶体管包括有源器件（RX）形成并且其上延伸有导线特征。该方法包括提供分析模型表示，其包括用于建模影响有源器件区域宽度的光刻火炬效应的功能; 并且从建模功能将有源器件区域宽度（deltaW加法器）的有效变化与距离RX区域的限定边缘的距离的函数相关联。然后，器件的晶体管紧凑型模型中的晶体管模型参数值被更新为包括要添加到内置deltaW值的ΔW加法器值。在模拟中使用的网表包括deltaW加法器值，以更精确地描述被建模的晶体管器件的特性，包括对晶体管器件参数的光刻拐角舍入效应的建模。

20. 发明授权

US07776695B2 Semiconductor device structure having low and high performance devices of same conductive type on same substrate 失效
标题翻译：具有相同基板上相同导电类型的低和高性能器件的半导体器件结构
公开(公告)号：US07776695B2
公开(公告)日：2010-08-17
申请号：US11306716
申请日：2006-01-09
申请人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
发明人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/0922 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.
摘要翻译：一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。

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