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11. 发明申请

US20100280256A1 PROCESS FOR PREPARING TRIAZOLONES 有权
标题翻译：制备三唑的方法
公开(公告)号：US20100280256A1
公开(公告)日：2010-11-04
申请号：US12791252
申请日：2010-06-01
申请人： Gary M. Lee , Jiang Zhu
发明人： Gary M. Lee , Jiang Zhu
IPC分类号： C07D249/12
CPC分类号： C07D249/12 , C07C17/18 , C07C45/004 , C07C253/14 , C07C253/30 , C07C25/18 , C07C47/55 , C07C255/54 , C07C255/56
摘要： The present process provides a improved method for the preparation of alkylsulfanyl substituted triazoles 2 which are useful intermediates in a new process for the preparation of triazolones 20.
摘要翻译：本发明方法提供了制备烷基硫烷基取代的三唑2的改进方法，它们是制备三唑酮20的新方法中有用的中间体。

12. 发明授权

US07745634B2 Process for preparing triazolones 有权
标题翻译：制备三唑酮的方法
公开(公告)号：US07745634B2
公开(公告)日：2010-06-29
申请号：US12156145
申请日：2008-05-30
申请人： Humberto Bartolome Arzeno , Gary M. Lee , Michael Martin , Keshab Sarma , Jiang Zhu
发明人： Humberto Bartolome Arzeno , Gary M. Lee , Michael Martin , Keshab Sarma , Jiang Zhu
IPC分类号： C07D249/12
CPC分类号： C07D249/12 , C07C17/18 , C07C45/004 , C07C253/14 , C07C253/30 , C07C25/18 , C07C47/55 , C07C255/54 , C07C255/56
摘要： The present process provides a improved method for the preparation of alkylsulfanyl substituted triazoles 2 which are useful intermediates in a new process for the preparation of triazolones 20.
摘要翻译：本发明方法提供了制备烷基硫烷基取代的三唑2的改进方法，它们是制备三唑酮20的新方法中有用的中间体。

13. 发明申请

US20090012304A1 Process for preparing triazolones 有权
标题翻译：制备三唑酮的方法
公开(公告)号：US20090012304A1
公开(公告)日：2009-01-08
申请号：US12156145
申请日：2008-05-30
申请人： Humberto Bartolome Arzeno , Gary M. Lee , Michael Martin , Keshab Sarma , Jiang Zhu
发明人： Humberto Bartolome Arzeno , Gary M. Lee , Michael Martin , Keshab Sarma , Jiang Zhu
IPC分类号： C07D249/12
CPC分类号： C07D249/12 , C07C17/18 , C07C45/004 , C07C253/14 , C07C253/30 , C07C25/18 , C07C47/55 , C07C255/54 , C07C255/56
摘要： The present process provides a improved method for the preparation of alkylsulfanyl substituted triazoles 2 which are useful intermediates in a new process for the preparation of triazolones 20.
摘要翻译：本发明方法提供了制备烷基硫烷基取代的三唑2的改进方法，它们是制备三唑酮20的新方法中有用的中间体。

14. 发明授权

US06801518B2 High speed cross point switch routing circuit with word-synchronous serial back plane 失效
公开(公告)号：US06801518B2
公开(公告)日：2004-10-05
申请号：US10074106
申请日：2002-02-12
申请人： John P. Mullaney , Gary M. Lee
发明人： John P. Mullaney , Gary M. Lee
IPC分类号： H04L1250
CPC分类号： H04L12/5601 , H04J3/0685 , H04L7/04 , H04L49/1576 , H04L49/3081 , H04L2012/5652 , H04L2012/5674 , H04L2012/5679 , H04L2012/5681 , H04L2012/5684 , H04Q11/0478
摘要： An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.

15. 发明授权

US5670666A Process for preparing intermediates for the synthesis of D1 antagonists 失效
标题翻译：制备D1拮抗剂合成中间体的方法
公开(公告)号：US5670666A
公开(公告)日：1997-09-23
申请号：US445404
申请日：1995-05-19
申请人： Donald Hou , Richard W. Draper , Gary M. Lee , Janet L. Mas
发明人： Donald Hou , Richard W. Draper , Gary M. Lee , Janet L. Mas
IPC分类号： C07C215/44 , C07C217/40 , C07C217/74 , C07D203/26 , C07D223/18 , C07D317/28 , C07D319/06
CPC分类号： C07C217/40 , C07C215/44 , C07C217/74 , C07D203/26 , C07D223/18 , C07B2200/07 , C07C2102/10
摘要： Disclosed are a process and intermediates of the formulae ##STR1## wherein X.sup.- is halide, BF.sub.4.sup.-, R.sup.3 SO.sub.3.sup.-, wherein R.sup.3 is C.sub.1 -C.sub.6 alkyl, CF.sub.3, C.sub.1 -C.sub.6 alkylphenyl or phenyl, and Q is a group of the formula ##STR2## wherein R is C.sub.1 -C.sub.6 alkyl; useful for preparing benzazepine intermediates of the formula ##STR3## These benzazepine intermediates are useful for preparing benzazepines having activity as selective D1 receptor antagonists.
摘要翻译：公开了式（Ⅰ）和（Ⅵ）的方法和中间体，其中X是卤化物，BF 4 - ，R 3 SO 3 - ，其中R 3是C 1 -C 6烷基，CF 3，C 1 -C 6烷基苯基或苯基，Q是基团其中R是C 1 -C 6烷基; 可用于制备下式的苯并氮杂中间体这些苯并氮杂中间体可用于制备具有选择性D1受体拮抗剂活性的苯并氮杂。

16. 发明授权

US4798979A Schottky diode logic for E-mode FET/D-mode FET VLSI circuits 失效
标题翻译：用于E型FET / D型FET VLSI电路的肖特基二极管逻辑
公开(公告)号：US4798979A
公开(公告)日：1989-01-17
申请号：US910545
申请日：1986-09-23
申请人： Gary M. Lee , Andrzej Peczalski
发明人： Gary M. Lee , Andrzej Peczalski
IPC分类号： H03K19/0944 , H03K19/003 , H03K19/0952 , H03K19/0956 , H03K19/017 , H03K17/04 , H03K19/094 , H03K19/20
CPC分类号： H03K19/0956 , H03K19/00384
摘要： A digital logic circuit using Schottky diodes as the nonlinear logic element, a single power supply and an E-mode MESFET as an inverter in the open drain configuration. Temperature compensation of the threshold voltage of the E-mode FET is provided. The circuit is particularly suited for use with a GaAs substrate.
摘要翻译：使用肖特基二极管作为非线性逻辑元件的数字逻辑电路，单电源和作为开漏配置的逆变器的E模MESFET。提供了E型FET的阈值电压的温度补偿。该电路特别适用于GaAs衬底。

17. 发明授权

US06700886B2 High speed cross point switch routing circuit with word-synchronous serial back plane 有权
标题翻译：具有字同步串行背板的高速交叉点开关路由电路
公开(公告)号：US06700886B2
公开(公告)日：2004-03-02
申请号：US10047166
申请日：2002-01-14
申请人： John P. Mullaney , Gary M. Lee
发明人： John P. Mullaney , Gary M. Lee
IPC分类号： H04L1250
CPC分类号： H04L12/5601 , H04J3/0685 , H04L7/04 , H04L49/1576 , H04L49/3081 , H04L2012/5652 , H04L2012/5674 , H04L2012/5679 , H04L2012/5681 , H04L2012/5684 , H04Q11/0478
摘要： An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.
摘要翻译：异步串行交叉点开关与多个收发器电路中的每一个字字同步。交叉点开关电路产生主位时钟和主字时钟信号。收发器电路使用时钟和数据恢复电路从输入的高速串行数据流中恢复主位时钟信号。恢复的位时钟信号用作定时信号，数据被串行化并发送到交叉点开关电路。发送到开关电路的数据流被锁定到主位时钟信号，使得串行数据流仅需要用数据恢复电路进行相位调整。为了恢复字定时，开关电路在链路初始化期间向对收发器发出对准字。收发器执行字对齐并建立本地字锁。然后使用本地字时钟将对准字重新发给开关电路。开关电路将接收的字时钟的边界与主字时钟进行比较，如果未对准，收发器将其发送的字移位一位，然后重试。必要边缘转换密度由开销比特提供，开销比特还指示在收发机和开关电路之间所确定的特殊命令字。流量控制信息使用开销位置从接收收发器路由到发送收发器，以便断言即将接收或不准备接收的流量控制信号。开销比特还提供关于连接请求和其他信息的信息。

18. 发明授权

US5502186A Process for preparing intermediates for the synthesis of D1 antagonists 失效
标题翻译：制备D1拮抗剂合成中间体的方法
公开(公告)号：US5502186A
公开(公告)日：1996-03-26
申请号：US447467
申请日：1995-05-23
申请人： Donald Hou , Richard W. Draper , Gary M. Lee , Janet L. Mas
发明人： Donald Hou , Richard W. Draper , Gary M. Lee , Janet L. Mas
IPC分类号： C07C217/70 , C07C271/16 , C07C271/22 , C07C271/24 , C07D223/14 , C07D263/06
CPC分类号： C07C271/24 , C07C217/70 , C07C271/16 , C07C271/22 , C07D223/14 , C07D263/06 , C07C2102/10
摘要： Disclosed are a process and intermediates of the formula ##STR1## wherein R is --CH.sub.3 or --C(O)--OR.sup.1, and R.sup.1 is C.sub.1 -C.sub.6 alkyl or --CH.sub.2 C.sub.6 H.sub.5 ; or the formula ##STR2## wherein: R.sup.2 is H or OH, R is --C(O)OR.sup.1 and R.sup.1 is C.sub.1 -C.sub.6 alkyl or --CH.sub.2 C.sub.6 H.sub.5, or where R.sup.2 is H, R can also be CH.sub.3 ; for preparing benzazepine intermediates of the formula ##STR3## The benzazepine intermediates are useful for preparing benzazepines having activity as selective D1 receptor antagonists.
摘要翻译：公开了式（IMAGE）的方法和中间体，其中R是-CH 3或-C（O）-OR 1，R 1是C 1 -C 6烷基或-CH 2 C 6 H 5; 或其中：R 2是H或OH，R是-C（O）OR 1，R 1是C 1 -C 6烷基或-CH 2 C 6 H 5，或者其中R 2是H，R也可以是CH 3; 用于制备下式的苯并氮杂中间体苯并吖庚因中间体可用于制备具有作为选择性D1受体拮抗剂活性的苯并氮杂。

19. 发明授权

US5353448A Water recycling system using spent recycled water with fresh water 失效
标题翻译：废水回收系统采用废水循环再用淡水
公开(公告)号：US5353448A
公开(公告)日：1994-10-11
申请号：US906418
申请日：1992-06-30
申请人： Gary M. Lee
发明人： Gary M. Lee
IPC分类号： E03C1/00 , E03C1/06 , A47K3/22
CPC分类号： E03C1/00 , E03C1/06
摘要： A water recycling system primarily adapted for use in shower facilities enabling the user to increase both the time duration of a shower and the quantity of water experienced by a user, by maintaining water in a semi-closed system, while both maintaining water and energy conservation. The system preferably operates with fresh and recirculated hot water. The system utilizes spent hot shower water located in the catchment area of a shower or tub and recycles this water to one or more spray heads located at or in the proximity of the regular water dispensing head or so-called "spray head" of that shower. A selected water temperature can be maintained by periodically introducing fresh water or continuously introducing the fresh water at a very low flow rate from a fresh water source, and mixing that water with the recycled water from a water catchment area. Recycled water can also be re-heated and issued again. The apparatus of the system may be provided with an adapter for quick connect and disconnect such that the apparatus can be moved from shower to shower. A manifold forming part of the apparatus includes a check valve arrangement to preclude gray water or spent hot water from entering into the water supply system.
摘要翻译：主要适用于淋浴设施的水回收系统，使用户能够通过在半封闭系统中保持水量同时增加淋浴持续时间和使用者体验到的水量，同时保持水和节能。该系统优选用新鲜和再循环的热水进行操作。该系统利用位于淋浴或浴盆的集水区域中的废热水淋浴，并将该水再循环到位于正常水分配头处或附近的一个或多个喷头或所述淋浴器的所谓“喷头” 。可以通过定期引入淡水或从淡水源以非常低的流速连续引入淡水并将水与来自集水区的再循环水混合来维持选定的水温。回收水也可以再次加热再次发出。系统的装置可以设置有用于快速连接和断开的适配器，使得装置可以从淋浴移动到淋浴。形成该装置的一部分的歧管包括止回阀装置，以排除灰水或废热水进入供水系统。

20. 发明授权

US4737837A Ring topology for an integrated circuit logic cell 失效
标题翻译：集成电路逻辑单元的环形拓扑
公开(公告)号：US4737837A
公开(公告)日：1988-04-12
申请号：US802566
申请日：1985-11-27
申请人： Gary M. Lee
发明人： Gary M. Lee
IPC分类号： H01L27/02 , H01L27/06 , H01L29/06 , H01L29/48 , H01L29/78 , H03K19/017
CPC分类号： H01L27/0605 , H01L27/0207 , H01L29/0692
摘要： An improved topology for a multi-input Boolean logic circuit whereby the circuit can be realized in integrated circuit form while consuming less area on the semiconductor wafer and exhibiting lower parasitic capacitance than equivalent integrated circuits using conventional topology. Rather than employing what might be described as an "in-line" topology of the prior art, a ring topology is used wherein adjacent MESFET's share a common region for source, drain, or source/drain contacts and wherein the amount of second level interconnect required is minimized.
摘要翻译：用于多输入布尔逻辑电路的改进的拓扑结构，由此电路可以以集成电路形式实现，同时消耗较少的半导体晶片上的面积并且比使用常规拓扑的等效集成电路具有更低的寄生电容。不是采用现有技术的“在线”拓扑结构，而是使用环形拓扑，其中相邻的MESFET共享用于源极，漏极或源极/漏极接触的公共区域，并且其中第二级互连所需的最小化。

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