专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07826563B2 High speed multi-modulus prescalar divider 有权
标题翻译：高速多模式预分频器
公开(公告)号：US07826563B2
公开(公告)日：2010-11-02
申请号：US11717262
申请日：2007-03-13
申请人： Hongming An , Simon Pang , Viet Linh Do
发明人： Hongming An , Simon Pang , Viet Linh Do
IPC分类号： H03D3/24
CPC分类号： H03L7/193 , G06F7/68 , H03K23/68
摘要： A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25.
摘要翻译：提供了一种用于多模式分割的系统和方法。该方法接受具有第一频率的输入第一信号，并将第一频率除以整数。利用具有第二频率的多个相位输出产生第二信号。使用菊花链寄存器控制器，相位输出被选择并作为具有频率的第三个信号提供。使用菊花链寄存器控制器选择相位输出包括将第三个信号作为时钟信号提供给具有以菊花链连接的输出的寄存器。然后，响应于时钟信号产生寄存器输出脉冲序列，并且从序列中选择寄存器输出脉冲以选择第二信号相位输出。通过使用8秒信号相位输出，获得第三个信号，频率等于第二个频率乘以以下数字之一：0.75,0.875,1,1125或1.25。

12. 发明授权

US07720189B2 System and method for automatic clock frequency acquisition 有权
标题翻译：自动时钟频率采集的系统和方法
公开(公告)号：US07720189B2
公开(公告)日：2010-05-18
申请号：US11595012
申请日：2006-11-09
申请人： Viet Linh Do , Mehmet Mustafa Eker , Simon Pang
发明人： Viet Linh Do , Mehmet Mustafa Eker , Simon Pang
IPC分类号： H03D3/24
CPC分类号： H03L7/113 , H03L7/093 , H03L7/0995 , H03L7/1974 , H04L7/033 , H04L7/0331
摘要： A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref1), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref1/n, where n is an integer≧1. The count for each sampling frequency is compared to the count for Fref1 (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref1, and the coarse clock frequency is set to Fc1 =Fref1/(x−1).
摘要翻译：提供了一种用于自动获取串行数据流时钟的系统和方法。该方法接收到具有未知时钟频率的串行数据流，并粗略地确定时钟频率。通过（最初）选择高频第一参考时钟（Fref1）粗略地确定频率，并且以等于Fref1 / n的多个采样频率对串行数据流的第一时间段中的数据转换次数进行计数，其中 n为整数≧1。将每个采样频率的计数与Fref1（n = 1）的计数进行比较。接下来，确定最高采样频率（n = x），其具有比Fref1更低的计数，并且将粗略时钟频率设置为Fc1 = Fref1 /（x-1）。

13. 发明申请

US20080225989A1 High speed multi-modulus prescalar divider 有权
标题翻译：高速多模式预分频器
公开(公告)号：US20080225989A1
公开(公告)日：2008-09-18
申请号：US11717262
申请日：2007-03-13
申请人： Hongming An , Simon Pang , Viet Linh Do
发明人： Hongming An , Simon Pang , Viet Linh Do
IPC分类号： H04L27/00
CPC分类号： H03L7/193 , G06F7/68 , H03K23/68
摘要： A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25.
摘要翻译：提供了一种用于多模式分割的系统和方法。该方法接受具有第一频率的输入第一信号，并将第一频率除以整数。利用具有第二频率的多个相位输出产生第二信号。使用菊花链寄存器控制器，相位输出被选择并作为具有频率的第三个信号提供。使用菊花链寄存器控制器选择相位输出包括将第三个信号作为时钟信号提供给具有以菊花链连接的输出的寄存器。然后，响应于时钟信号产生寄存器输出脉冲序列，并且从序列中选择寄存器输出脉冲以选择第二信号相位输出。通过使用8秒信号相位输出，获得第三个信号，频率等于第二个频率乘以以下数字之一：0.75,0.875,1,1125或1.25。

14. 发明申请

US20080224735A1 Frequency Synthesis Rational Division 有权
标题翻译：频率综合理科
公开(公告)号：US20080224735A1
公开(公告)日：2008-09-18
申请号：US12120027
申请日：2008-05-13
申请人： Viet Linh Do , Simon Pang , Hongming An , Jim Lew
发明人： Viet Linh Do , Simon Pang , Hongming An , Jim Lew
IPC分类号： H03B21/00
CPC分类号： H03L7/1976 , G06F7/68 , H03K23/486
摘要： A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q
摘要翻译：提供了一种使用合理划分来合成信号频率的系统和方法。该方法接受参考频率值和合成频率值。响应于将合成频率值除以参考频率值，确定整数值分子（dp）和整数值分母（dq）。该方法降低了dp / dq与整数N的比值和p / q（dp / dq = N（p / q））的比值，其中p / q <1（十进制）。分子（p）和分母（q）被提供给灵活的累加器模块，因此产生除数。 N与k位商相加以创建除数。在锁相环（PLL）中，除数和参考信号用于产生频率等于合成频率值的合成信号。

15. 发明授权

US08443023B2 Frequency synthesis rational division 有权
标题翻译：频率综合理性分割
公开(公告)号：US08443023B2
公开(公告)日：2013-05-14
申请号：US12120027
申请日：2008-05-13
申请人： Viet Linh Do , Simon Pang , Hongming An , Jim Lew
发明人： Viet Linh Do , Simon Pang , Hongming An , Jim Lew
IPC分类号： G06F1/02
CPC分类号： H03L7/1976 , G06F7/68 , H03K23/486
摘要： A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q
摘要翻译：提供了一种使用合理划分来合成信号频率的系统和方法。该方法接受参考频率值和合成频率值。响应于将合成频率值除以参考频率值，确定整数值分子（dp）和整数值分母（dq）。该方法降低了dp / dq与整数N的比值和p / q（dp / dq = N（p / q））的比率，其中p / q <1（十进制）。分子（p）和分母（q）被提供给灵活的累加器模块，因此产生除数。 N与k位商相加以创建除数。在锁相环（PLL）中，除数和参考信号用于产生频率等于合成频率值的合成信号。

16. 发明授权

US08121242B2 Frequency lock stability in device using overlapping VCO bands 有权
标题翻译：使用重叠VCO频带的设备中的频率锁定稳定性
公开(公告)号：US08121242B2
公开(公告)日：2012-02-21
申请号：US12388024
申请日：2009-02-18
申请人： Viet Linh Do , Mehmet Mustafa Eker , Simon Pang
发明人： Viet Linh Do , Mehmet Mustafa Eker , Simon Pang
IPC分类号： H03D3/24
CPC分类号： H04L7/0004 , H03L7/0891 , H03L7/113 , H03L7/1976 , H04L7/033
摘要： A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range.
摘要翻译：提供了一种用于使用重叠压控振荡器（VCO）频带的接收机中的频率锁定稳定性的系统和方法。接受输入通信信号并选择初始VCO。使用锁相环（PLL）和初始VCO，获取输入通信信号的频率，并测量初始VCO的采集信号调谐电压。然后，初始VCO被分离并且多个相邻频带VCO被顺序地接合。测量每个VCO的获取的信号调谐电压，并且选择能够使用最接近预定调谐电压范围的中点的获取的信号调谐电压来产生输入通信信号频率的最终VCO。

17. 发明授权

US07936853B2 False frequency lock detector 有权
标题翻译：虚拟锁定检测器
公开(公告)号：US07936853B2
公开(公告)日：2011-05-03
申请号：US11983675
申请日：2007-11-09
申请人： Simon Pang , Viet Linh Do , Mehmet Mustafa Eker
发明人： Simon Pang , Viet Linh Do , Mehmet Mustafa Eker
IPC分类号： H04L7/00
CPC分类号： H04L7/0083 , H03L7/095 , H03L2207/14 , Y10S331/02
摘要： A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate—to detect if the clock signal is incorrectly locked to the first rate.
摘要翻译：提供了用于检测时钟和数据恢复（CDR）设备中的假时钟频率锁定的系统和方法。该方法以第一速率接收数字原始数据信号，并计算原始数据信号中的边沿转换，创建原始计数。时钟信号也以第二速率被接受。时钟信号是从原始数据信号恢复的定时参考。原始数据信号以响应于时钟信号的速率被采样，产生采样信号。在采样信号中计数边沿转换，创建采样计数。然后，将原始计数与采样计数进行比较，以确定第一速率是否等于第二速率。该方法用于确定第二速率是否小于第一速率 - 以检测时钟信号是否被错误地锁定到第一速率。

18. 发明申请

US20090157791A1 FLEXIBLE ACCUMULATOR FOR RATIONAL DIVISION 有权
标题翻译：灵活的累加器用于分类
公开(公告)号：US20090157791A1
公开(公告)日：2009-06-18
申请号：US11954325
申请日：2007-12-12
申请人： Viet Linh Do , Simon Pang
发明人： Viet Linh Do , Simon Pang
IPC分类号： G06F7/487
CPC分类号： G06F7/535 , G06F2207/5353
摘要： A system and method are provided for rational division. The method accepts accepting a binary numerator and a binary denominator. A binary first sum is created of the numerator and a binary first count from a previous cycle. A binary first difference is created between the first sum and the denominator. In response to comparing the first sum with the denominator, and first carry bit is generated and added to a first binary sequence. The first binary sequence is used to generate a k-bit quotient. Typically, the denominator value is larger than the numerator value. In one aspect, the numerator and denominator form a rational number. Alternately, the numerator may be an n-bit bit value formed as either a repeating or non-repeating sequence, and the denominator is an (n+1)-bit number with a decimal value of 2(n+1).
摘要翻译：提供了一种合理划分的系统和方法。该方法接受接受二进制分子和二进制分母。由分子创建二进制第一和，并从上一个循环创建二进制第一个计数。在第一个总和和分母之间创建二进制的第一个差异。响应于将第一和与分母进行比较，并且生成第一进位位并将其相加到第一二进制序列。第一个二进制序列用于生成k比特商。通常，分母值大于分子值。一方面，分子和分母形成一个有理数。或者，分子可以是形成为重复序列或非重复序列的n位比特值，分母是小数值为2（n + 1）的（n + 1）位数字。

19. 发明授权

US08489664B2 Single clock cycle first order limited accumulator for supplying weighted corrections 有权
标题翻译：单时钟周期第一阶有限累加器用于提供加权校正
公开(公告)号：US08489664B2
公开(公告)日：2013-07-16
申请号：US12399861
申请日：2009-03-06
申请人： Viet Linh Do , Wei Fu , Arash Farhoodfar
发明人： Viet Linh Do , Wei Fu , Arash Farhoodfar
IPC分类号： G06F11/00
CPC分类号： G06F7/535 , G06F2207/5353
摘要： A method is provided for first order accumulation in a single clock cycle. The method accepts a limited gain value and an accumulated value stored in a previous clock cycle. Using combinational logic, the limited gain value is summed with the accumulated value. If the summed value is between upper and lower limits, a non-weighted correction signal is supplied, and the summed value is the storage value. If the summed value is greater than the upper limit, a positive weighting is supplied, the (upper limit+1) is subtracted from the summed value, and the result is the storage value. If the summed value is less than the lower limit, then a negative weighting is supplied, the lower limit is subtracted from the summed value, and the result is the storage value. The storage value is loaded in memory for use as the accumulated value in the subsequent clock cycle.
摘要翻译：提供了在单个时钟周期中用于一阶累积的方法。该方法接受在前一个时钟周期中存储的有限增益值和累加值。使用组合逻辑，将有限增益值与累积值相加。如果总和值在上限和下限之间，则提供非加权校正信号，并且求和值为存储值。如果总和值大于上限，则提供正加权，从求和值中减去（上限+ 1），结果为存储值。如果总和值小于下限，则提供负加权，从求和值中减去下限，结果为存储值。存储值被加载到存储器中以用作随后时钟周期中的累加值。

20. 发明申请

US20080304610A1 Frequency Reacquisition in a Clock and Data Recovery Device 有权
标题翻译：时钟和数据恢复设备中的频率重新采集
公开(公告)号：US20080304610A1
公开(公告)日：2008-12-11
申请号：US12194744
申请日：2008-08-20
申请人： Viet Linh Do , Mehmet Mustafa Eker
发明人： Viet Linh Do , Mehmet Mustafa Eker
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H03L7/081 , H03L7/113 , H03L7/18 , H03L7/1976
摘要： A system and method are provided for reacquiring a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous communication signal having an input data frequency. In response to acquiring the phase of the input data frequency, a synthesized signal is generated having an output frequency. Also as a result of acquiring the input data frequency, a frequency ratio value is selected. The output frequency is divided by the selected frequency ratio value, creating a divisor signal having a divisor frequency, which is compared to a reference signal frequency. In response to the comparison, the frequency ratio value is saved in a tangible memory medium. In response to losing phase-lock with the communication signal, the frequency ratio value is retrieved from memory. After acquiring the input data frequency, the phase of the communication signal is reacquired.
摘要翻译：提供了一种用于在时钟和数据恢复（CDR）设备频率合成器中重新获取非同步通信信号的系统和方法。该方法最初获取具有输入数据频率的非同步通信信号的相位。响应于获取输入数据频率的相位，产生具有输出频率的合成信号。另外，作为获取输入数据频率的结果，选择频率比值。将输出频率除以所选择的频率比值，产生具有除数频率的除数信号，与参考信号频率进行比较。响应于比较，频率比值被保存在有形存储介质中。响应于通信信号丢失相位锁定，从存储器检索频率比值。获取输入数据频率后，重新获取通信信号的相位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式