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11. 发明授权

US08458438B2 System, method and computer program product for providing quiesce filtering for shared memory 有权
标题翻译：用于为共享存储器提供静默滤波的系统，方法和计算机程序产品
公开(公告)号：US08458438B2
公开(公告)日：2013-06-04
申请号：US12037897
申请日：2008-02-26
申请人： Lisa C. Heller , Ute Gaertner , Dan F. Greiner , Damian L. Osisek , Donald W. Schmidt
发明人： Lisa C. Heller , Ute Gaertner , Dan F. Greiner , Damian L. Osisek , Donald W. Schmidt
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A system, method and computer program product for providing quiesce filtering for shared memory. The method includes receiving a shared-memory quiesce request at a processor. The request includes a donor zone. The processor includes translation look aside buffer one (TLB1). It is determined that the shared-memory request can be filtered by the processor if there not any shared memory entries in the TLB1 and the donor zone is not equal to a current zone of the processor and the processor is not running in host mode. The shared-memory quiesce request is filtered in response to the determining.
摘要翻译：一种用于为共享存储器提供静默滤波的系统，方法和计算机程序产品。该方法包括在处理器处接收共享存储器静默请求。请求包括捐助者区域。处理器包括翻译后备缓冲区（TLB1）。如果TLB1中没有任何共享存储器条目，并且供体区域不等于处理器的当前区域并且处理器未在主机模式下运行，则确定共享存储器请求可被处理器过滤。响应于确定，对共享内存静默请求进行过滤。

12. 发明授权

US06766434B2 Method for sharing a translation lookaside buffer between CPUs 有权
标题翻译：在CPU之间共享翻译后备缓冲区的方法
公开(公告)号：US06766434B2
公开(公告)日：2004-07-20
申请号：US10126239
申请日：2002-04-19
申请人： Ute Gaertner , Norbert Hagspiel , Frank Lehnert , Erwin Pfeffer , Kerstin Schelm
发明人： Ute Gaertner , Norbert Hagspiel , Frank Lehnert , Erwin Pfeffer , Kerstin Schelm
IPC分类号： G06F1208
CPC分类号： G06F12/1027
摘要： The present invention generally relates to shared-memory multiprocessor systems, such as IBM ESA/390 or RS/6000 systems, and deals more particularly with a method and system for sharing a second-level translation lookaside buffer (TLB 2) between several CPUs (30a, . . . 30d) for improving the performance and reducing the chip area required to buffer the results of virtual-to-absolute address translations. The inventive TLB2 organization comprises several small arrays (32a, . . . 32d) dedicated to particular CPUs, providing an interface to a major array (21), which is shared between the CPUs. The dedicated arrays 32a, . . . 32d) are required to fulfill the architected constraints and link several CPUs to the commonly used shared array (21).
摘要翻译：本发明一般涉及诸如IBM ESA / 390或RS / 6000系统的共享存储器多处理器系统，更具体地涉及用于在多个CPU之间共享第二级转换后备缓冲器（TLB 2）的方法和系统（ 30a，... 30d），用于提高性能并减少缓冲虚拟到绝对地址转换结果所需的芯片面积。本发明的TLB2组织包括专用于特定CPU的几个小阵列（32a，...，32d），提供与CPU之间共享的主阵列（21）的接口。专用阵列32a，。。。 32d）需要满足架构约束并将多个CPU链接到常用的共享阵列（21）。

13. 发明授权

US08332614B2 System, method and computer program product for providing a programmable quiesce filtering register 有权
标题翻译：用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品
公开(公告)号：US08332614B2
公开(公告)日：2012-12-11
申请号：US13372603
申请日：2012-02-14
申请人： Lisa C. Heller , Harald Boehm , Ute Gaertner , Jennifer A. Navarro , Timothy J. Slegel
发明人： Lisa C. Heller , Harald Boehm , Ute Gaertner , Jennifer A. Navarro , Timothy J. Slegel
IPC分类号： G06F12/10
CPC分类号： G06F9/4812
摘要： Storing translation lookaside buffer (TLB) entries are in a TLB1 at the processor. The TLB1 includes entries associated with main storage accesses of programs executing in a guest mode in a current zone and entries associated with main storage accesses of firmware executing in a host mode. A quiesce interruption request is received at the processor that includes a requesting zone indicator. The processor is either executing in the host mode and has no zone or in the guest mode with the current zone. The requesting zone indicator and the contents of a programmable filtering register that indicates exceptions to filtering performed by the processor is used to determine if filtering should be performed. The quiesce interruption request may be filtered based on the requesting zone indicator even after the mode switches from the guest mode to the host mode.
摘要翻译：存储翻译后备缓冲区（TLB）条目位于处理器的TLB1中。 TLB1包括与在当前区域中以访客模式执行的程序的主存储访问相关联的条目和与以主机模式执行的固件的主存储访问相关联的条目。在包括请求区域指示符的处理器处接收到静默中断请求。处理器正在主机模式下执行，并且没有区域，或者在访问模式下使用当前区域。请求区域指示符和指示处理器执行的过滤异常的可编程过滤寄存器的内容用于确定是否应执行过滤。即使模式从客户模式切换到主机模式，也可以基于请求区域指示符来过滤停顿中断请求。

14. 发明申请

US20090216995A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING QUIESCE FILTERING FOR SHARED MEMORY 有权
标题翻译：用于提供共享存储器的QUIESCE过滤的系统，方法和计算机程序产品
公开(公告)号：US20090216995A1
公开(公告)日：2009-08-27
申请号：US12037897
申请日：2008-02-26
申请人： Lisa C. Heller , Ute Gaertner , Dan F. Greiner , Damian L. Osisek , Donald W. Schmidt
发明人： Lisa C. Heller , Ute Gaertner , Dan F. Greiner , Damian L. Osisek , Donald W. Schmidt
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A system, method and computer program product for providing quiesce filtering for shared memory. The method includes receiving a shared-memory quiesce request at a processor. The request includes a donor zone. The processor includes translation look aside buffer one (TLB1). It is determined that the shared-memory request can be filtered by the processor if there not any shared memory entries in the TLB1 and the donor zone is not equal to a current zone of the processor and the processor is not running in host mode. The shared-memory quiesce request is filtered in response to the determining.
摘要翻译：一种用于为共享存储器提供静默滤波的系统，方法和计算机程序产品。该方法包括在处理器处接收共享存储器静默请求。请求包括捐助者区域。处理器包括翻译后备缓冲区（TLB1）。如果TLB1中没有任何共享存储器条目，并且供体区域不等于处理器的当前区域并且处理器未在主机模式下运行，则确定共享存储器请求可被处理器过滤。响应于确定，对共享内存静默请求进行过滤。

15. 发明授权

US06418522B1 Translation lookaside buffer for virtual memory systems 有权
标题翻译：用于虚拟内存系统的翻译后备缓冲区
公开(公告)号：US06418522B1
公开(公告)日：2002-07-09
申请号：US09501741
申请日：2000-02-11
申请人： Ute Gaertner , John MacDougall , Erwin Pfeffer , Kerstin Schelm
发明人： Ute Gaertner , John MacDougall , Erwin Pfeffer , Kerstin Schelm
IPC分类号： G06F1210
CPC分类号： G06F12/1027 , G06F2212/681
摘要： The basic idea comprised of the present invention is to provide a translation lookaside buffer (TLB) arrangement which advantageously uses two buffers, a small first level TLB1 and a larger second level TLB2. The second level TLB feeds address information to the first level TLB when the desired virtual address is not contained in the first level TLB. According to the invention the second level TLB is structured advantageously comprising two n-way set-associative sub-units of which one, a higher level unit covers some higher level address translation levels and the other one, a lower level unit, covers some lower level translation level. According to the present invention, some address information holds some number of middle level virtual address (MLVA) bits, i.e., 8 bits, for example, being able to serve as an index address covering the address range of the higher level sub-unit. Thus, the same information is used as a tag information in the lower-level sub-unit and is used herein as a quick reference in any look-up operation in order to find the absolute address of the concerned virtual address. Further, the commonly used status bits, like; e.g., valid bits, are used in both TLB structures, too.
摘要翻译：由本发明构成的基本思想是提供一种有利地使用两个缓冲器，小的第一级TLB1和较大的第二级TLB2的翻译后备缓冲器（TLB）装置。当所需的虚拟地址不包含在第一级TLB中时，第二级TLB将地址信息馈送到第一级TLB。根据本发明，第二级TLB有利地包括两个n路组合关联子单元，其中一个较高级别单元覆盖一些较高级地址转换级别，而另一级单元覆盖一些较低级别的地址转换级别级别翻译水平。根据本发明，一些地址信息例如保持一些中间虚拟地址（MLVA）位，即8位，能够用作覆盖上位子单元的地址范围的索引地址。因此，相同的信息用作下级子单元中的标签信息，并且在本文中用作任何查找操作中的快速参考，以便找到相关虚拟地址的绝对地址。此外，常用的状态位，如; 例如有效位也用在两个TLB结构中。

16. 发明授权

US5978957A Very fast pipelined shifter element with parity prediction 失效
标题翻译：具有奇偶校验预测的非常快速的流水线移位器元件
公开(公告)号：US5978957A
公开(公告)日：1999-11-02
申请号：US765003
申请日：1997-07-14
申请人： Wilhelm Haller , Klaus Getzlaff , Erwin Pfeffer , Ute Gaertner , Gunter Gerwig
发明人： Wilhelm Haller , Klaus Getzlaff , Erwin Pfeffer , Ute Gaertner , Gunter Gerwig
IPC分类号： G06F11/10 , G06F5/01
CPC分类号： G06F5/015 , G06F11/10
摘要： A shifting structure and method which separates a shifting operation into partial shifts which may be executed in different pipeline staged is described herein. In a first pipe stage, an operand is read out and at least one partial shift is accomplished by placing the operand or parts thereof into registers coupled to a shift unit. The shift unit, in a second pipe stage, finalizes the shifting operation executing the remaining partial shifts, thereby reducing the time required for the total shifting operation. A control string is derived in the shift unit based on the shift amount to correct the output of the shifted result as well as providing for parity prediction therefor.
摘要翻译： PCT No.PCT / EP95 / 01456 Sec。 371日期1997年7月14日 102（e）日期1997年7月14日PCT提交1995年4月18日PCT公布。公开号WO96 / 33455 日期1996年10月24日这里描述了将移动操作分离成可以在不同流水线分段中执行的部分班次的换档结构和方法。在第一管道级中，读出操作数，并且通过将操作数或其部分放入耦合到移位单元的寄存器来实现至少一个部分移位。在第二管段中的换档单元完成执行剩余部分换挡的换档操作，从而减少了总换档操作所需的时间。基于移位量，在移位单元中导出控制串，以校正移位结果的输出以及为此进行奇偶校验。

17. 发明授权

US08966221B2 Translating translation requests having associated priorities 有权
标题翻译：翻译具有相关优先级的翻译请求
公开(公告)号：US08966221B2
公开(公告)日：2015-02-24
申请号：US13165013
申请日：2011-06-21
申请人： Ute Gaertner , Thomas Koehler
发明人： Ute Gaertner , Thomas Koehler
IPC分类号： G06F12/00 , G06F13/00 , G06F12/10 , G06F12/08
CPC分类号： G06F12/1027 , G06F12/0855
摘要： A lookup operation is performed in a translation look aside buffer based on a first translation request as current translation request, wherein a respective absolute address is returned to a corresponding requestor for the first translation request as translation result in case of a hit. A translation engine is activated to perform at least one translation table fetch in case the current translation request does not hit an entry in the translation look aside buffer, wherein the translation engine is idle waiting for the at least one translation table fetch to return data, reporting the idle state of the translation engine as lookup under miss condition and accepting a currently pending translation request as second translation request, wherein a lookup under miss sequence is performed in the translation look aside buffer based on said second translation request.
摘要翻译：在基于第一翻译请求的翻译旁边缓冲器中执行查找操作作为当前翻译请求，其中相应的绝对地址在命中情况下作为翻译结果返回给第一翻译请求的对应请求者。翻译引擎被激活以执行至少一个转换表提取，以防当前转换请求没有到达翻译旁边缓冲器中的条目，其中翻译引擎空闲等待至少一个转换表提取返回数据，将所述翻译引擎的空闲状态报告为在未命中条件下的查找，并接受当前待处理的转换请求作为第二转换请求，其中在所述翻译旁边缓冲器中基于所述第二翻译请求执行在未命中序列下的查找。

18. 发明授权

US08407701B2 Facilitating quiesce operations within a logically partitioned computer system 失效
标题翻译：在逻辑分区的计算机系统中促进停顿操作
公开(公告)号：US08407701B2
公开(公告)日：2013-03-26
申请号：US12822818
申请日：2010-06-24
申请人： Ute Gaertner , Lisa C. Heller , Jennifer A. Navarro
发明人： Ute Gaertner , Lisa C. Heller , Jennifer A. Navarro
IPC分类号： G06F9/455 , G06F9/46 , G06F1/24 , G06F3/00 , G06F9/44 , G06F13/00
CPC分类号： G06F9/52
摘要： A facility is provided for processing to distinguish between a full conventional (or total system) quiesce request within a logically partitioned computer system, which requires all processors of the computer system to remain quiesced for the duration of the quiesce-related operation, and a new early-release conventional quiesce request, which is associated with fast-quiesce request utilization. In accordance with the facility, once all processors have quiesced responsive to a pending quiesce request sequence, the processors are allowed to block early-release conventional quiesce interrupts and to continue processing if there is no total system quiesce request in the pending quiesce request sequence.
摘要翻译：提供了一种用于处理以区分逻辑分区的计算机系统内的完全常规（或整个系统）静默请求的设施，其要求计算机系统的所有处理器在静默相关操作期间保持静止，并且新的早期发布常规静默请求，这与快速静默请求利用相关。根据该设施，一旦所有处理器对待处理的静默请求序列作出响应，则处理器被允许阻止早期释放常规停顿中断，并且如果在暂停停顿请求序列中没有总系统静默请求，则继续处理。

19. 发明申请

US20120144154A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER 有权
标题翻译：用于提供可编程QUIESCE FILTERING寄存器的系统，方法和计算机程序产品
公开(公告)号：US20120144154A1
公开(公告)日：2012-06-07
申请号：US13372603
申请日：2012-02-14
申请人： Lisa C. Heller , Harald Boehm , Ute Gaertner , Timothy J. Slegel , Jennifer A. Navarro
发明人： Lisa C. Heller , Harald Boehm , Ute Gaertner , Timothy J. Slegel , Jennifer A. Navarro
IPC分类号： G06F12/10
CPC分类号： G06F9/4812
摘要： Storing translation lookaside buffer (TLB) entries are in a TLB1 at the processor. The TLB1 includes entries associated with main storage accesses of programs executing in a guest mode in a current zone and entries associated with main storage accesses of firmware executing in a host mode. A quiesce interruption request is received at the processor that includes a requesting zone indicator. The processor is either executing in the host mode and has no zone or in the guest mode with the current zone. The requesting zone indicator and the contents of a programmable filtering register that indicates exceptions to filtering performed by the processor is used to determine if filtering should be performed. The quiesce interruption request may be filtered based on the requesting zone indicator even after the mode switches from the guest mode to the host mode.
摘要翻译：存储翻译后备缓冲区（TLB）条目位于处理器的TLB1中。 TLB1包括与在当前区域中以访客模式执行的程序的主存储访问相关联的条目和与以主机模式执行的固件的主存储访问相关联的条目。在包括请求区域指示符的处理器处接收到静默中断请求。处理器正在主机模式下执行，并且没有区域，或者在访问模式下使用当前区域。请求区域指示符和指示处理器执行的过滤异常的可编程过滤寄存器的内容用于确定是否应执行过滤。即使模式从客户模式切换到主机模式，也可以基于请求区域指示符来过滤停顿中断请求。

20. 发明申请

US20090217269A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING MULTIPLE QUIESCE STATE MACHINES 有权
标题翻译：用于提供多种状态机器的系统，方法和计算机程序产品
公开(公告)号：US20090217269A1
公开(公告)日：2009-08-27
申请号：US12037734
申请日：2008-02-26
申请人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
发明人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
IPC分类号： G06F9/46
CPC分类号： G06F12/1027 , G06F9/52 , G06F12/10 , G06F2212/682 , G06F2212/683
摘要： A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time.
摘要翻译：一种用于提供多个静默状态机的系统，方法和计算机程序产品。该系统包括第一控制器，其包括用于处理第一静默请求的逻辑。该系统还包括第二控制器，其包括用于处理第二静默请求的逻辑。处理第二停顿请求的全部或一部分与处理第一停顿请求的时间重叠。因此，多个静默请求可能在系统中同时处于活动状态。

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