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11. 发明授权

US6147913A Data transmission circuitry of a synchronous semiconductor memory device 有权
标题翻译：同步半导体存储器件的数据传输电路
公开(公告)号：US6147913A
公开(公告)日：2000-11-14
申请号：US513621
申请日：2000-02-25
申请人： Hak-Soo Yu , Su-Chul Kim
发明人： Hak-Soo Yu , Su-Chul Kim
IPC分类号： G11C11/413 , G11C7/10 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/417 , G11C7/00
CPC分类号： G11C11/4093 , G11C11/4076 , G11C11/4096 , G11C7/1006 , G11C7/1072 , G11C7/22
摘要： A synchronous memory comprises a memory cell array having a plurality of memory cells; a clock control circuit for receiving a first clock signal, a second clock signal, and a third clock signal, and for generating an internal clock signal, a plurality of control signals, and a plurality of flag signals. The memory includes a first register circuit for storing a plurality of input data bits in response to the internal clock signal and to the control signals; a second register circuit for storing the flag signals in response to the internal clock signal and the control signals; a write drive circuit for writing the input data bits passing through the first register circuit into the memory cell array in response to the flag signals during a write cycle; a sense amplifier circuit coupled to the memory cell array, an address comparator circuit for receiving read and write address signals and for generating a first, a second, and a third combination signals; and a switching circuit for transferring the input data bits passing through the first register circuit and the flag signals passing through the second register circuit to output terminals of the device.
摘要翻译：同步存储器包括具有多个存储器单元的存储单元阵列; 时钟控制电路，用于接收第一时钟信号，第二时钟信号和第三时钟信号，并用于产生内部时钟信号，多个控制信号和多个标志信号。存储器包括用于响应于内部时钟信号和控制信号而存储多个输入数据位的第一寄存器电路; 第二寄存器电路，用于响应于内部时钟信号和控制信号而存储标志信号; 写入驱动电路，用于在写入周期期间响应于标志信号，将通过第一寄存器电路的输入数据位写入存储单元阵列; 耦合到存储单元阵列的读出放大器电路，用于接收读和写地址信号并用于产生第一，第二和第三组合信号的地址比较器电路; 以及用于将通过第一寄存器电路的输入数据位和通过第二寄存器电路的标志信号传送到器件的输出端的开关电路。

12. 发明授权

US09268636B2 Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices 有权
标题翻译：半导体存储器件包括纠错电路和操作半导体存储器件的方法
公开(公告)号：US09268636B2
公开(公告)日：2016-02-23
申请号：US13910591
申请日：2013-06-05
申请人： Hoi-ju Chung , Su-A Kim , Mu-Jin Seo , Hak-Soo Yu , Jae-Youn Youn , Hyo-Jin Choi
发明人： Hoi-ju Chung , Su-A Kim , Mu-Jin Seo , Hak-Soo Yu , Jae-Youn Youn , Hyo-Jin Choi
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F11/073 , G06F11/076 , G06F11/079 , G06F11/0793 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F11/1076 , G11C11/409 , G11C29/52 , G11C29/783
摘要： A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.
摘要翻译：存储器控制器包括：控制器输入/输出电路，被配置为输出第一命令以读取第一数据，并输出第二命令以读取第一数据的纠错部分。存储装置包括：误差检测器，数据存储电路和纠错电路。错误检测器被配置为响应于第一命令来检测从存储器单元读取的数据中的错误位数。如果检测到的错误比特数大于或等于第一阈值，则数据存储电路被配置为存储读取数据。误差校正电路被配置为校正存储的数据。

13. 发明授权

US08547766B2 Area-efficient data line layouts to suppress the degradation of electrical characteristics 有权
标题翻译：区域高效的数据线布局，以抑制电气特性的恶化
公开(公告)号：US08547766B2
公开(公告)日：2013-10-01
申请号：US12659883
申请日：2010-03-24
申请人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C11/4097
摘要： A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.
摘要翻译：数据线布局包括在存储单元阵列区域上的层上沿着第一方向布置的列选择线以及沿着该层的第一方向布置的数据线，数据线连接在I / O读出放大器和I / O之间垫

14. 发明申请

US20130060985A1 DEVICE CAPABLE OF ADOPTING AN EXTERNAL MEMORY 有权
标题翻译：能够采用外部存储器的设备
公开(公告)号：US20130060985A1
公开(公告)日：2013-03-07
申请号：US13606551
申请日：2012-09-07
申请人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
发明人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
IPC分类号： G06F13/16
CPC分类号： G06F13/16 , G06F13/1694 , G06F13/385
摘要： A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.
摘要翻译：设备包括存储器控制器，耦合到存储器控制器的存储器总线，内部存储器和外部存储器连接单元。内部存储器可以通过存储器总线直接连接到存储器控制器。外部存储器连接单元可以通过存储器总线中的一部分信号线将外部存储器直接连接到存储器控制器，并且可以产生指示外部存储器是否连接到外部存储器连接单元的标志信号。

15. 发明授权

US07616512B2 Semiconductor memory device with hierarchical bit line structure 有权
公开(公告)号：US07616512B2
公开(公告)日：2009-11-10
申请号：US12347233
申请日：2008-12-31
申请人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
发明人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
IPC分类号： G11C7/00
CPC分类号： G11C11/417 , G11C7/18 , G11C8/12
摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

16. 发明申请

US20080165559A1 Data line layout and line driving method in semiconductor memory device 有权
标题翻译：半导体存储器件中的数据线布局和线驱动方法
公开(公告)号：US20080165559A1
公开(公告)日：2008-07-10
申请号：US12006502
申请日：2008-01-03
申请人： Nam-Seog Kim , Hak-Soo Yu , Uk-Rae Cho
发明人： Nam-Seog Kim , Hak-Soo Yu , Uk-Rae Cho
IPC分类号： G11C5/06 , G11C7/10
CPC分类号： G11C5/063 , G11C7/1051 , G11C7/1069 , G11C7/18 , G11C11/417
摘要： A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number of first data lines are connected to each sub mat. The second data lines are disposed in a smaller quantity than the number of the first data lines so as to form a hierarchy with respect to the first data lines. The third data line is disposed to form a hierarchy with respect to the second data lines, and transfers data provided through the second data lines to a data latch. The first data line driver is connected between the first data lines and the second data lines, and performs a logical ORing operation for output of the first data lines so as to drive a corresponding second data line. The second data line driver is connected between the second data lines and the third data line, and performs a logical ORing operation for output of the second data lines so as to drive the third data line.
摘要翻译：数据线布局结构包括多个第一数据线，第二数据线，第三数据线，第一数据线驱动器和第二数据线驱动器。多个第一数据线连接到存储器垫中的子垫，使得预定数量的第一数据线连接到每个子垫。第二数据线的布置量比第一数据线的数量少，从而形成相对于第一数据线的层次。第三数据线被布置成相对于第二数据线形成层级，并且将通过第二数据线提供的数据传送到数据锁存器。第一数据线驱动器连接在第一数据线和第二数据线之间，并且执行用于输出第一数据线的逻辑“或”运算，以驱动对应的第二数据线。第二数据线驱动器连接在第二数据线和第三数据线之间，并且执行用于输出第二数据线的逻辑“或”运算，以驱动第三数据线。

17. 发明申请

US20070115710A1 Semiconductor memory device with hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体存储器件
公开(公告)号：US20070115710A1
公开(公告)日：2007-05-24
申请号：US11480447
申请日：2006-07-05
申请人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
发明人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
IPC分类号： G11C5/06
CPC分类号： G11C11/417 , G11C7/18 , G11C8/12
摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.
摘要翻译：半导体存储器件具有分层位线结构。半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通孔的数量基本上减小。

18. 发明授权

US6166969A Method and apparatus for a level shifter for use in a semiconductor memory device 失效
标题翻译：一种用于半导体存储器件的电平转换器的方法和装置
公开(公告)号：US6166969A
公开(公告)日：2000-12-26
申请号：US345582
申请日：1999-06-30
申请人： Byoung-Cheol Song , Hak-Soo Yu , Kwang-Jin Lee
发明人： Byoung-Cheol Song , Hak-Soo Yu , Kwang-Jin Lee
IPC分类号： G11C11/409 , G11C7/06 , G11C11/34 , H03K19/0185 , G11C7/00
CPC分类号： G11C7/06 , H03K19/018521
摘要： Disclosed is a level shifter that can receive and convert a first signal that can have various voltage logic levels to a second signal having internal voltage logic levels. The level shifter includes first and second ascending/descending circuits, where the first ascend/descending circuit receives the first signal and the second ascend/descending circuit receives an inverted first signal. Each ascend/descending circuit is operable to descend a high logic level of the received signal to a low output voltage level and ascend a low logic level of the received signal to a high output voltage level. The output voltages from the first and second ascending/descending circuits are input to a sense amplifier that amplifies the difference between the output voltages in order to generate the internal voltage logic levels of the second signal. The first and second ascending/descending circuits buffer their respective received signals using the high logic level of the input signal as a supply voltage. The same principles are also applicable to the level shifting from internal voltage logic levels to external voltage logic levels.
摘要翻译：公开了一种电平转换器，其可以接收和转换可以具有各种电压逻辑电平的第一信号到具有内部电压逻辑电平的第二信号。电平移位器包括第一和第二上升/下降电路，其中第一上升/下降电路接收第一信号，第二上升/下降电路接收反相的第一信号。每个上升/下降电路可操作以将接收信号的高逻辑电平降低到低输出电压电平，并将接收信号的低逻辑电平上升到高输出电压电平。来自第一和第二上升/下降电路的输出电压被输入到放大输出电压之间的差的读出放大器，以产生第二信号的内部电压逻辑电平。第一和第二上升/下降电路使用输入信号的高逻辑电平作为电源电压来缓冲它们各自的接收信号。相同的原理也适用于从内部电压逻辑电平转换到外部电压逻辑电平的电平。

19. 发明授权

US08488399B2 Semiconductor devices having a three-dimensional stacked structure and methods of de-skewing data therein 有权
标题翻译：具有三维堆叠结构的半导体器件和其中的数据失真的方法
公开(公告)号：US08488399B2
公开(公告)日：2013-07-16
申请号：US13108130
申请日：2011-05-16
申请人： Hak-Soo Yu , Sang-Bo Lee , Hong-Sun Hwang , Dong-Hyun Sohn
发明人： Hak-Soo Yu , Sang-Bo Lee , Hong-Sun Hwang , Dong-Hyun Sohn
IPC分类号： G11C7/00
CPC分类号： G11C5/02 , G11C5/063 , G11C7/222 , G11C8/14 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0061 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50012 , G11C2213/71
摘要： A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.
摘要翻译：具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作。因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。

20. 发明申请

US20110286254A1 Semiconductor Devices Having a Three-Dimensional Stacked Structure and Methods of De-Skewing Data Therein 有权
标题翻译：具有三维堆叠结构的半导体器件及其中的数据偏移方法
公开(公告)号：US20110286254A1
公开(公告)日：2011-11-24
申请号：US13108130
申请日：2011-05-16
申请人： Hak-Soo Yu , Sang-Bo Lee , Hong-Sun Hwang , Dong-Hyun Sohn
发明人： Hak-Soo Yu , Sang-Bo Lee , Hong-Sun Hwang , Dong-Hyun Sohn
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/063 , G11C7/222 , G11C8/14 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0061 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50012 , G11C2213/71
摘要： A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.
摘要翻译：具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作。因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。

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