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1. 发明授权

US07616512B2 Semiconductor memory device with hierarchical bit line structure 有权
公开(公告)号：US07616512B2
公开(公告)日：2009-11-10
申请号：US12347233
申请日：2008-12-31
申请人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
发明人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
IPC分类号： G11C7/00
CPC分类号： G11C11/417 , G11C7/18 , G11C8/12
摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

2. 发明申请

US20070115710A1 Semiconductor memory device with hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体存储器件
公开(公告)号：US20070115710A1
公开(公告)日：2007-05-24
申请号：US11480447
申请日：2006-07-05
申请人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
发明人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
IPC分类号： G11C5/06
CPC分类号： G11C11/417 , G11C7/18 , G11C8/12
摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.
摘要翻译：半导体存储器件具有分层位线结构。半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通孔的数量基本上减小。

3. 发明授权

US07489570B2 Semiconductor memory device with hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体存储器件
公开(公告)号：US07489570B2
公开(公告)日：2009-02-10
申请号：US11480447
申请日：2006-07-05
申请人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
发明人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
IPC分类号： G11C7/00
CPC分类号： G11C11/417 , G11C7/18 , G11C8/12
摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.
摘要翻译：半导体存储器件具有分层位线结构。半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通道的数量大幅减少。

4. 发明授权

US07656723B2 Semiconductor memory device with hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体存储器件
公开(公告)号：US07656723B2
公开(公告)日：2010-02-02
申请号：US12347239
申请日：2008-12-31
申请人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
发明人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
IPC分类号： G11C7/22
CPC分类号： G11C11/417 , G11C7/18 , G11C8/12
摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.
摘要翻译：半导体存储器件具有分层位线结构。半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通孔的数量基本上减小。

5. 发明申请

US20080165559A1 Data line layout and line driving method in semiconductor memory device 有权
标题翻译：半导体存储器件中的数据线布局和线驱动方法
公开(公告)号：US20080165559A1
公开(公告)日：2008-07-10
申请号：US12006502
申请日：2008-01-03
申请人： Nam-Seog Kim , Hak-Soo Yu , Uk-Rae Cho
发明人： Nam-Seog Kim , Hak-Soo Yu , Uk-Rae Cho
IPC分类号： G11C5/06 , G11C7/10
CPC分类号： G11C5/063 , G11C7/1051 , G11C7/1069 , G11C7/18 , G11C11/417
摘要： A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number of first data lines are connected to each sub mat. The second data lines are disposed in a smaller quantity than the number of the first data lines so as to form a hierarchy with respect to the first data lines. The third data line is disposed to form a hierarchy with respect to the second data lines, and transfers data provided through the second data lines to a data latch. The first data line driver is connected between the first data lines and the second data lines, and performs a logical ORing operation for output of the first data lines so as to drive a corresponding second data line. The second data line driver is connected between the second data lines and the third data line, and performs a logical ORing operation for output of the second data lines so as to drive the third data line.
摘要翻译：数据线布局结构包括多个第一数据线，第二数据线，第三数据线，第一数据线驱动器和第二数据线驱动器。多个第一数据线连接到存储器垫中的子垫，使得预定数量的第一数据线连接到每个子垫。第二数据线的布置量比第一数据线的数量少，从而形成相对于第一数据线的层次。第三数据线被布置成相对于第二数据线形成层级，并且将通过第二数据线提供的数据传送到数据锁存器。第一数据线驱动器连接在第一数据线和第二数据线之间，并且执行用于输出第一数据线的逻辑“或”运算，以驱动对应的第二数据线。第二数据线驱动器连接在第二数据线和第三数据线之间，并且执行用于输出第二数据线的逻辑“或”运算，以驱动第三数据线。

6. 发明授权

US07697314B2 Data line layout and line driving method in semiconductor memory device 有权
标题翻译：半导体存储器件中的数据线布局和线驱动方法
公开(公告)号：US07697314B2
公开(公告)日：2010-04-13
申请号：US12006502
申请日：2008-01-03
申请人： Nam-Seog Kim , Hak-Soo Yu , Uk-Rae Cho
发明人： Nam-Seog Kim , Hak-Soo Yu , Uk-Rae Cho
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/1051 , G11C7/1069 , G11C7/18 , G11C11/417
摘要： A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number of first data lines are connected to each sub mat. The second data lines are disposed in a smaller quantity than the number of the first data lines so as to form a hierarchy with respect to the first data lines. The third data line is disposed to form a hierarchy with respect to the second data lines, and transfers data provided through the second data lines to a data latch. The first data line driver is connected between the first data lines and the second data lines, and performs a logical ORing operation for output of the first data lines so as to drive a corresponding second data line. The second data line driver is connected between the second data lines and the third data line, and performs a logical ORing operation for output of the second data lines so as to drive the third data line.
摘要翻译：数据线布局结构包括多个第一数据线，第二数据线，第三数据线，第一数据线驱动器和第二数据线驱动器。多个第一数据线连接到存储器垫中的子垫，使得预定数量的第一数据线连接到每个子垫。第二数据线的布置量比第一数据线的数量少，从而形成相对于第一数据线的层次。第三数据线被布置成相对于第二数据线形成层级，并且将通过第二数据线提供的数据传送到数据锁存器。第一数据线驱动器连接在第一数据线和第二数据线之间，并且执行用于输出第一数据线的逻辑“或”运算，以驱动对应的第二数据线。第二数据线驱动器连接在第二数据线和第三数据线之间，并且执行用于输出第二数据线的逻辑“或”运算，以驱动第三数据线。

7. 发明授权

US06366149B1 Delay circuit having variable slope control and threshold detect 有权
标题翻译：具有可变斜率控制和阈值检测的延迟电路
公开(公告)号：US06366149B1
公开(公告)日：2002-04-02
申请号：US09649389
申请日：2000-08-28
申请人： Jong-Cheol Lee , Hak-Soo Yu
发明人： Jong-Cheol Lee , Hak-Soo Yu
IPC分类号： H03H1126
CPC分类号： H03K5/13
摘要： A delay circuit in accordance with the present invention provides high-resolution changes in the time delay by utilizing a slope controller that generates an intermediate signal having sloping edges in response to edges in an input signal. A delay time controller generates an output signal having edges that begin when the level of the intermediate signal reaches a certain level. The overall time delay of the delay circuit can be varied by varying the slope of the edges of the intermediate signal, or by varying the level of the intermediate signal at which the delay time controller begins generating an edge in the output signal, or by varying both parameters. The slope controller and delay time controller can be realized with a plurality of tri-state inverters coupled in parallel for operating responsive to one or more select signals. By implementing the inverters with pull-up and pull-down transistors having different sizes, the overall time delay can be varied with very high resolution.
摘要翻译：根据本发明的延迟电路通过利用产生具有响应于输入信号中的边缘的倾斜边缘的中间信号的斜率控制器来提供时间延迟中的高分辨率变化。延迟时间控制器产生具有当中间信号的电平达到一定水平时开始的边沿的输出信号。可以通过改变中间信号的边沿的斜率，或通过改变延迟时间控制器开始在输出信号中产生边沿的中间信号的电平，或者通过改变延迟电路的整个时间延迟两个参数。斜率控制器和延迟时间控制器可以通过多个并联耦合的三态反相器来实现，以响应于一个或多个选择信号进行操作。通过用具有不同尺寸的上拉和下拉晶体管实现逆变器，总体时间延迟可以以非常高的分辨率变化。

8. 发明授权

US09058897B2 Semiconductor memory device storing memory characteristic information, memory module and memory system having the same, and operating method thereof 有权
标题翻译：存储存储器特性信息的半导体存储器件，具有该存储器特性信息的存储器模块和存储器系统及其操作方法
公开(公告)号：US09058897B2
公开(公告)日：2015-06-16
申请号：US13670065
申请日：2012-11-06
申请人： Hak-Soo Yu , Joo-Sun Choi , Hong-Sun Hwan
发明人： Hak-Soo Yu , Joo-Sun Choi , Hong-Sun Hwan
IPC分类号： G11C5/02 , G11C11/4063 , G11C14/00 , G11C16/06 , G11C11/406
CPC分类号： G11C11/4063 , G11C11/406 , G11C14/00 , G11C14/0018 , G11C16/06 , G11C29/783 , G11C2211/4061
摘要： A semiconductor memory device includes a cell array including a plurality of regions accessed by first addresses, where the plurality of regions including at least two groups of regions having respectively different memory characteristics. The device further includes a nonvolatile array for nonvolatile storage of group information indicative of which of the least two groups each of the plurality of regions belongs.
摘要翻译：半导体存储器件包括一个单元阵列，该单元阵列包括由第一地址访问的多个区域，其中多个区域包括具有不同存储特性的至少两组区域。该装置还包括用于非易失性存储指示多个区域中的至少两个组中的哪一个属于哪个组的非易失性阵列。

9. 发明申请

US20120087177A1 SEMICONDUCTOR MEMORY DEVICE FOR DATA SENSING 有权
标题翻译：用于数据传感的半导体存储器件
公开(公告)号：US20120087177A1
公开(公告)日：2012-04-12
申请号：US13238553
申请日：2011-09-21
申请人： Sua KIM , Chul-Woo Park , Hong-Sun Hwang , Hak-Soo Yu
发明人： Sua KIM , Chul-Woo Park , Hong-Sun Hwang , Hak-Soo Yu
IPC分类号： G11C11/24
CPC分类号： G11C11/4091 , G11C11/4099
摘要： A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.
摘要翻译：半导体存储器件包括存储单元和第一参考存储单元。存储单元包括第一开关元件和用于存储数据的第一电容器。第一开关元件由第一字线控制，并且具有连接到第一电容器的第一端子的第一端子和连接到第一位线的第二端子。第一电容器具有用于接收第一板电压的第二端子。第一参考存储单元包括第一参考开关元件和第一电容器。第一开关元件由第一参考字线控制，并且具有连接到第一参考电容器的第一端子的第一端子和连接到第二位线的第二端子。第一参考电容器具有接收与第一板电压不同的第一参考板电压的第二端子。

10. 发明授权

US06304495B1 Logic interface circuit and semiconductor memory device using this circuit 有权
标题翻译：逻辑接口电路和使用该电路的半导体存储器件
公开(公告)号：US06304495B1
公开(公告)日：2001-10-16
申请号：US09576936
申请日：2000-05-22
申请人： Suk-San Kim , Hak-Soo Yu
发明人： Suk-San Kim , Hak-Soo Yu
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C7/1048
摘要： A logic interface circuit and a semiconductor memory device to which the logic interface circuit is applied, the circuit comprising: logic gate means having pull up means and pull down means which respectively responds to one or more input signals to pull up and pull down an output terminal; reverse current preventing means connected between a first supply voltage and the pull up means for preventing current from reversing from the pull up means to the first supply voltage; pre-charging means connected in parallel to the reverse current preventing means for responding to the output signal generated from the output terminal to pre-charge a common point of the reverse current preventing means and the pull up means to the first supply voltage; and reverse current preventing and voltage boosting means connected between the second supply voltage and the output terminal for responding to the first supply voltage to turn off to prevent current from reversing from the output terminal to the second supply voltage if the first supply voltage is higher than the second supply voltage, and for responding to one or more input signals to turn on to set up the output terminal to the second supply voltage if the first supply voltage is lower than the second supply voltage, thereby enabling to shift levels of the supply voltage by adding a simple circuit to logic gates like inverter, NAND gate or NOR gate.
摘要翻译：逻辑接口电路和应用逻辑接口电路的半导体存储器件，该电路包括：具有上拉装置和下拉装置的逻辑门装置，其分别响应于一个或多个输入信号以上拉和下拉输出终奌站; 连接在第一电源电压和上拉装置之间的反向电流防止装置，用于防止电流从上拉装置反转到第一电源电压; 预充电装置并联连接到反向电流防止装置，用于响应从输出端产生的输出信号，以将反向电流防止装置和上拉装置的公共点预充电到第一电源电压; 以及连接在所述第二电源电压和所述输出端子之间的反向电流防止和升压装置，用于响应于所述第一电源电压以关闭以防止电流从所述输出端子反转到所述第二电源电压，如果所述第一电源电压高于第二电源电压，并且如果第一电源电压低于第二电源电压，则响应于一个或多个输入信号而导通以将输出端子设置为第二电源电压，从而使电源电压的电平通过向逻辑门添加一个简单的电路，如反相器，NAND门或NOR门。

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