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11. 发明授权

US4949145A Homo-junction bipolar transistor having high base concentration and suitable for low temperature operation 失效
标题翻译：具有高碱浓度并适用于低温操作的同相双极晶体管
公开(公告)号：US4949145A
公开(公告)日：1990-08-14
申请号：US253228
申请日：1988-10-04
申请人： Kazuo Yano , Masaaki Aoki , Toshiaki Masuhara , Katsuhiro Shimohigashi
发明人： Kazuo Yano , Masaaki Aoki , Toshiaki Masuhara , Katsuhiro Shimohigashi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/36 , H01L29/66 , H01L29/732
CPC分类号： H01L29/66992 , H01L27/0623 , H01L29/36
摘要： In a homo-junction bipolar transistor suitable for a low temperature operation below 200.degree.K. (particularly below 77 K), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3. The impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.
摘要翻译：在适用于低于200°K（特别是低于77K）的低温操作的同相双极晶体管中，本征基区的杂质浓度的最大值设定为至少1×1018 / cm3。发射极区域的杂质浓度设定为比该最大值低的值。因此，可以降低基极电阻并且可以进行高速运行。此外，在本征基极区域中产生带隙变窄，并且可以将低温操作中的共发射极电流增益保持在足够的值。当这种同相双极晶体管与半导体衬底表面上的互补绝缘栅场效应晶体管一起形成时，即使在低温操作中也可以获得能够进行高速运行的Bi-CMOS器件。

12. 发明授权

US5041892A Homo-junction bipolar transistor having high base concentration and suitable for low temperature operation 失效
标题翻译：具有高碱浓度并适用于低温操作的同相双极晶体管
公开(公告)号：US5041892A
公开(公告)日：1991-08-20
申请号：US522826
申请日：1990-05-14
申请人： Kazuo Yano , Masaaki Aoki , Toshiaki Masuhara , Katsuhiro Shimohigashi
发明人： Kazuo Yano , Masaaki Aoki , Toshiaki Masuhara , Katsuhiro Shimohigashi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/36 , H01L29/66 , H01L29/732
CPC分类号： H01L29/66992 , H01L27/0623 , H01L29/36
摘要： In a homo-junction bipolar transistor suitable for a low temperature operation below 200 K. (particularly below 77 K.), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3 and the impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and a high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.

13. 发明授权

US5148387A Logic circuit and data processing apparatus using the same 失效
标题翻译：逻辑电路及使用其的数据处理装置
公开(公告)号：US5148387A
公开(公告)日：1992-09-15
申请号：US480674
申请日：1990-02-15
申请人： Kazuo Yano , Koichiro Ishibashi , Tetsuya Nakagawa , Katsuhiro Shimohigashi , Osamu Minato
发明人： Kazuo Yano , Koichiro Ishibashi , Tetsuya Nakagawa , Katsuhiro Shimohigashi , Osamu Minato
IPC分类号： G06F7/50 , G06F7/501
CPC分类号： G06F7/5016
摘要： A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are connected to the sixth FET. The first and second FETs are connected to the first input node. The third and fourth FETs are connected to the second node. A first signal is supplied to the first input node. A second signal is supplied to gate electrodes of the first and fourth FETs. A signal having a phase opposite to the second signal is supplied to gate electrodes of the second and third FETs. A third signal is supplied to the second input node. One signal selected from the first, second and the third signals is supplied to the gate electrode of the fifth FET. A signal having a phase opposite to the signal supplied to the gate electrode of the fifth FET is supplied to the gate electrode of the sixth FET. An output signal related to the first, second and third input signals is generated from the output node. The output signal is, for example, a carry output signal or alternatively a majority decision logic output signal.
摘要翻译：逻辑电路包括第一，第二，第三，第四，第五和第六场效应晶体管或FET，输入节点和输出节点。第五和第六FET连接到输出节点。第一和第三FET连接到第五FET。第二和第四FET连接到第六FET。第一和第二FET连接到第一输入节点。第三和第四FET连接到第二节点。第一信号被提供给第一输入节点。向第一和第四FET的栅电极提供第二信号。具有与第二信号相反的相位的信号被提供给第二和第三FET的栅电极。第三信号被提供给第二输入节点。从第一，第二和第三信号中选择的一个信号被提供给第五FET的栅电极。具有与提供给第五FET的栅电极的信号相反的相位的信号被提供给第六FET的栅电极。从输出节点生成与第一，第二和第三输入信号有关的输出信号。输出信号例如是进位输出信号或多数决定逻辑输出信号。

14. 发明授权

US4992677A High speed MOSFET output buffer with low noise 失效
标题翻译：高速MOSFET输出缓冲器，噪音低
公开(公告)号：US4992677A
公开(公告)日：1991-02-12
申请号：US325439
申请日：1989-03-20
申请人： Koichiro Ishibashi , Osamu Minato , Katsuhiro Shimohigashi
发明人： Koichiro Ishibashi , Osamu Minato , Katsuhiro Shimohigashi
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K17/166 , H03K19/00361
摘要： A semiconductor integrated circuit includes: a data output terminal; a first semiconductor element connected between a first operating potential point and the data output terminal; a second semiconductor element connected between the data output terminal and a second operating potential point; first control means connected to a control input terminal of the first semiconductor element; second control means connected to a control input terminal of the second semiconductor element; first generating means for generating a first predetermined voltage; and second generating means for generating a second predetermined voltage higher than the first predetermined voltage. When voltage at the data output terminal is higher than the second predetermined voltage, the first control means controls the first semiconductor element to be in the OFF-state, and the second control means controls the second semiconductor element to be in the ON-state to lower the voltage of the data output terminal to the second predetermined voltage. On the other hand, in the case where the voltage of the data output terminal is lower than that of the first predetermined voltage, the output of the first control means controls the first semiconductor element so that it is in the ON-state and the output of the second control means controls the second semiconductor element so that it is in the OFF-state so as to raise the voltage of the data output terminal to the first predetermined voltage.
摘要翻译：半导体集成电路包括：数据输出端子; 连接在第一操作电位点和数据输出端之间的第一半导体元件; 连接在数据输出端和第二工作电位之间的第二半导体元件; 连接到第一半导体元件的控制输入端的第一控制装置; 连接到第二半导体元件的控制输入端子的第二控制装置; 用于产生第一预定电压的第一产生装置; 以及第二产生装置，用于产生高于第一预定电压的第二预定电压。当数据输出端子的电压高于第二预定电压时，第一控制装置控制第一半导体元件处于截止状态，第二控制装置将第二半导体元件控制在导通状态将数据输出端子的电压降低到第二预定电压。另一方面，在数据输出端子的电压低于第一预定电压的电压的情况下，第一控制装置的输出控制第一半导体元件使其处于导通状态并且输出所述第二控制装置控制所述第二半导体元件使其处于截止状态，以将所述数据输出端子的电压升高到所述第一预定电压。

15. 发明授权

US5134581A Highly stable semiconductor memory with a small memory cell area 失效
标题翻译：高度稳定的半导体存储器具有小的存储单元面积
公开(公告)号：US5134581A
公开(公告)日：1992-07-28
申请号：US604469
申请日：1990-10-29
申请人： Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu
发明人： Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu
IPC分类号： G11C11/412 , G11C11/419 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412 , G11C11/419 , H01L27/1108
摘要： In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W.sub.DEFF /L.sub.DEFF)/(W.sub.TEFF /L.sub.TEFF)
摘要翻译：为了获得具有小单元区域的高度稳定的SRAM单元，单元比率R被设置为R =（WDEFF / LDEFF）/（WTEFF / LTEFF）<3，其中LDEFF和WDEFF表示有效信道长度，并且有效沟道宽度分别为两个驱动MOSFET 3和4，LTEFF和WTEFF分别表示两个传输MOSFET 5和6的有效沟道长度和有效沟道宽度。此外，流入有源负载MOSFET 1和2的最大电流IR被设置为大于当跨栅极施加阈值电压时流入驱动器MOSFET 5的电流IL（1×10 -8 A），并且 MOSFET 5.一对有源负载MOSFET 1和2堆叠在驱动器MOSFET 3和4以及传输MOSFET 5和6上。

16. 发明授权

US5629898A Dynamic memory device, a memory module, and a method of refreshing a dynamic memory device 失效
标题翻译：动态存储器件，存储器模块和刷新动态存储器件的方法
公开(公告)号：US5629898A
公开(公告)日：1997-05-13
申请号：US607977
申请日：1996-02-29
申请人： Youji Idei , Katsuhiro Shimohigashi , Masakazu Aoki , Hiromasa Noda , Katsuyuki Sato , Hidetoshi Iwai , Makoto Saeki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Osamu Tsuchiya
发明人： Youji Idei , Katsuhiro Shimohigashi , Masakazu Aoki , Hiromasa Noda , Katsuyuki Sato , Hidetoshi Iwai , Makoto Saeki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Osamu Tsuchiya
IPC分类号： G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C11/406 , G11C2211/4016 , G11C2211/4061
摘要： A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.
摘要翻译：对与动态存储单元的最短信息保持时间对应的周期脉冲进行计数，以形成分配给多个字线的刷新地址。从刷新地址计数器输出的进位信号由分频器分频。对于分配有刷新地址的所述多个字线中的每一个，对应于定时器的输出脉冲的短周期中的一个或与来自分频器的分频脉冲相对应的长周期中的一个作为刷新时间设置信息被存储在存储电路中。根据存储在存储电路中的刷新时间设定信息，由刷新地址执行的存储器单元刷新动作对每个字线进行有效或无效，并且刷新时间设定信息本身被分频器的输出脉冲无效。

17. 发明授权

US5430681A Memory cartridge and its memory control method 失效
标题翻译：内存盒及其内存控制方式
公开(公告)号：US5430681A
公开(公告)日：1995-07-04
申请号：US266870
申请日：1994-07-05
申请人： Ken Sugawara , Shigeru Sakairi , Mikio Matoba , Toshio Sasaki , Katsuhiro Shimohigashi , Katsutaka Kimura
发明人： Ken Sugawara , Shigeru Sakairi , Mikio Matoba , Toshio Sasaki , Katsuhiro Shimohigashi , Katsutaka Kimura
IPC分类号： G11C5/14 , G11C8/18 , G11C11/406 , G11C11/4074 , G11C11/40
CPC分类号： G11C8/18 , G11C11/406 , G11C11/4074 , G11C5/141 , G11C5/143 , G11C5/147
摘要： A memory cartridge having a plurality of dynamic memory units includes an access conversion circuit which converts a static access signal into its inverted signal and an access control circuit which controllably switches between a signal for refreshing each dynamic unit and a signal for external access. The memory cartridge also includes a power switching circuit which switches power from an internal power supply to an external power supply when the memory cartridge is mounted to an external device.
摘要翻译：具有多个动态存储单元的存储器盒包括将静态访问信号转换为其反相信号的访问转换电路和可控地在用于刷新每个动态单元的信号和用于外部访问的信号之间切换的访问控制电路。存储盒还包括一个电源切换电路，当存储盒被安装到外部设备时，电源切换电路将电源从内部电源切换到外部电源。

18. 发明授权

US5331596A Address multiplexed dynamic RAM having a test mode capability 失效
标题翻译：地址复用动态RAM具有测试模式能力
公开(公告)号：US5331596A
公开(公告)日：1994-07-19
申请号：US887802
申请日：1992-05-26
申请人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
发明人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
IPC分类号： G11C11/401 , G01R31/317 , G11C29/00 , G11C29/14 , G11C29/46 , G11C11/407
CPC分类号： G11C29/46 , G01R31/31701
摘要： An address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability is provided. The test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.
摘要翻译：提供具有正常操作模式和测试模式能力的地址多路复用动态随机存取存储器（RAM）。响应于行地址选通（＆upbar＆R）和列地址选通（＆upbar＆C）信号和写使能（＆upbar＆W）信号的特定信号电平组合，启动测试模式。由于在动态RAM的正常操作模式中不使用与实现测试模式相关的信号电平组合，因此不需要额外的外部终端。该动态RAM在动态RAM的输入侧和输出侧都采用多路复用电路，该复用电路在正常操作期间通过来自解码器的选择信号以及在测试模式期间通过允许访问的测试信号通过测试电路在所有公共补充数据线上的数据，以便确定正在读出的用于测试的数据是否一致或不一致。

19. 发明授权

US5119332A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5119332A
公开(公告)日：1992-06-02
申请号：US515345
申请日：1990-04-30
申请人： Katsuhiro Shimohigashi , Hiroo Masuda , Hiroshi Kawamoto
发明人： Katsuhiro Shimohigashi , Hiroo Masuda , Hiroshi Kawamoto
IPC分类号： G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/108
CPC分类号： H01L27/108 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/10805 , H01L2924/0002 , H01L2924/3011
摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed to a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
摘要翻译：单元存储单元型的动态RAM集成电路设置有多条数据线，读出放大器，以与数据线相交的方式设置的多条字线，以及设置在数据线上的存储单元数据线与字线之间的交点。 RAM包括P型半导体衬底和形成在衬底中的N型阱区。存储单元设置在阱内，并且连接到日期线的读出放大器被构造成形成在半导体衬底中的一对N沟道MOSFET和形成在阱区中的一对P沟道MOSFET 。

20. 发明授权

US4811299A Dynamic RAM device having a separate test mode capability 失效
标题翻译：具有单独测试模式能力的动态RAM设备
公开(公告)号：US4811299A
公开(公告)日：1989-03-07
申请号：US41070
申请日：1987-04-22
申请人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
发明人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
IPC分类号： G11C11/401 , G01R31/317 , G11C29/00 , G11C29/14 , G11C29/46 , G11C7/00 , G11C8/00
CPC分类号： G11C29/46 , G01R31/31701
摘要： Disclosed is a dynamic RAM device capable of initiating and cancelling the test mode in response to the combinations of the row address and column address strobe signals with the write enable signal, which combinations are left unused in the normal operating mode, instead of increasing the number of external control signals.
摘要翻译：公开了一种动态RAM装置，其能够响应于行地址和列地址选通信号与写使能信号的组合而启动和取消测试模式，这些组合在正常操作模式下不被使用，而不是增加数量的外部控制信号。

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