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11. 发明授权

US07859055B2 Thin film transistor 有权
标题翻译：薄膜晶体管
公开(公告)号：US07859055B2
公开(公告)日：2010-12-28
申请号：US11989287
申请日：2006-06-01
申请人： Hiroshi Matsukizono , Tadayoshi Miyamoto
发明人： Hiroshi Matsukizono , Tadayoshi Miyamoto
IPC分类号： H01L27/12 , H01L33/00
CPC分类号： H01L29/4908 , H01L29/06 , H01L29/66757 , H01L29/78675
摘要： To provide: a thin film transistor which can be operated with a low threshold and has a high transistor withstand voltage; a production method of the thin film transistor; and a semiconductor device, an active matrix substrate, and a display device, each including such a thin film transistor. The present invention is a thin film transistor including a semiconductor layer, a gate insulating film, a gate electrode on a substrate in this order, wherein a cross section of the semiconductor layer has a forward tapered shape; the gate insulating film covers a top surface and a side surface of the semiconductor layer; and the gate insulating film has a multilayer structure including a silicon oxide film on a semiconductor layer side and a film made of a material with a dielectric constant higher than a dielectric constant of silicon oxide on a gate electrode side; the gate insulating film satisfies 0.5≦B/A where a thickness of the gate insulating film on the top surface of the semiconductor layer is defined as A and a thickness of the gate insulating film on the side surface of the semiconductor layer is defined as B.
摘要翻译：提供：可以以低阈值操作并具有高晶体管耐受电压的薄膜晶体管; 薄膜晶体管的制造方法; 以及各自包括这种薄膜晶体管的半导体器件，有源矩阵基板和显示器件。本发明是一种薄膜晶体管，其包括半导体层，栅极绝缘膜，基板上的栅电极，其中半导体层的横截面具有正锥形形状; 栅极绝缘膜覆盖半导体层的顶表面和侧表面; 并且所述栅极绝缘膜具有包括半导体层侧的氧化硅膜的多层结构和由栅电极侧的介电常数高于氧化硅的介电常数的材料构成的膜; 栅绝缘膜满足0.5＆nlE; B / A，其中半导体层的顶表面上的栅极绝缘膜的厚度被定义为A，并且半导体层的侧表面上的栅极绝缘膜的厚度被定义为 B.

12. 发明授权

US06835675B2 Laser-irradiation method and laser-irradiation device 失效
标题翻译：激光照射方法和激光照射装置
公开(公告)号：US06835675B2
公开(公告)日：2004-12-28
申请号：US10316605
申请日：2002-12-10
申请人： Shunpei Yamazaki , Satoshi Teramoto , Naoto Kusumoto , Takeshi Fukunaga , Setsuo Nakajima , Tadayoshi Miyamoto , Atsushi Yoshinouchi
发明人： Shunpei Yamazaki , Satoshi Teramoto , Naoto Kusumoto , Takeshi Fukunaga , Setsuo Nakajima , Tadayoshi Miyamoto , Atsushi Yoshinouchi
IPC分类号： H01L2126
CPC分类号： G10L17/22 , H01L27/1285 , H01L29/66757 , H01L29/66765 , H01L29/78621 , H04M3/2281 , H04M3/229 , H04M3/382 , H04M3/385 , H04M2201/40 , H04Q3/0016
摘要： A laser-irradiation method which comprises a process for fabricating a semiconductor device, comprising: a first step of forming a thin film amorphous semiconductor on a substrate having an insulating surface; a second step of modifying the thin film amorphous semiconductor into a crystalline thin film semiconductor by irradiating a pulse-type linear light and/or by applying a heat treatment; a third step of implanting an impurity element which imparts a one conductive type to the crystalline thin film semiconductor; and a fourth step of activating the impurity element by irradiating a pulse-type linear light and/or by applying a heat treatment; wherein the peak value, the peak width at half height, and the threshold width of the laser energy in the second and the fourth steps above are each distributed within a range of approximately ±3% of the standard value. Also claimed is a laser irradiation device which realizes the method above.
摘要翻译：一种激光照射方法，包括制造半导体器件的工艺，包括：在具有绝缘表面的衬底上形成薄膜非晶半导体的第一步骤; 通过照射脉冲型线性光和/或通过施加热处理将薄膜非晶半导体改性成晶体薄膜半导体的第二步骤; 将赋予一种导电类型的杂质元素注入晶体薄膜半导体的第三步骤; 以及通过照射脉冲型线性光和/或通过施加热处理来激活杂质元素的第四步骤; 其中上述第二和第四步骤中的峰值，半高峰值宽度和激光能量的阈值宽度各自分布在标准值的约±3％的范围内。还要求保护的是实现上述方法的激光照射装置。

13. 发明授权

US06603518B1 Liquid crystal display capable of reducing amount of return light to TFT and manufacturing method therefor 有权
标题翻译：能够减少向TFT返回光量的液晶显示器及其制造方法
公开(公告)号：US06603518B1
公开(公告)日：2003-08-05
申请号：US09618802
申请日：2000-07-18
申请人： Tadayoshi Miyamoto , Toshihiko Degawa
发明人： Tadayoshi Miyamoto , Toshihiko Degawa
IPC分类号： G02F1136
CPC分类号： G02F1/136209 , G02F2202/104
摘要： There is provided a liquid crystal display device, as well as a manufacturing method therefor, capable of preventing characteristic deterioration of TFTs by reducing the amount of return light incident on the TFTs. A light interception thin film 2 is composed of a silicide film formed on a transparent substrate 1 and a polysilicon film formed so as to cover a top of the silicide film, and a polysilicon film 3 is formed so as to cover a top of the light interception thin film 2. Then, by making up a light interception film from the light interception thin film 2 and the polysilicon film 3, the light interception effect on a TFT-use polysilicon layer 5 formed over the light interception film with interposition of the transparent insulation film 4, and enough thermal resistance and adhesion can be obtained in the TFT manufacturing process.
摘要翻译：提供了一种能够通过减少入射到TFT上的返回光量来防止TFT的特性劣化的液晶显示装置及其制造方法。光截取薄膜2由形成在透明基板1上的硅化物膜和形成为覆盖硅化物膜的顶部的多晶硅膜构成，并且形成多晶硅膜3以覆盖光的顶部截取薄膜2.然后，通过从遮光薄膜2和多晶硅薄膜3构成遮光膜，对形成于遮光膜上的TFT用多晶硅层5的遮光效果插入透明绝缘膜4，并且在TFT制造工艺中可以获得足够的热阻和粘附性。

14. 发明授权

US5696003A Method for fabricating a semiconductor device using a catalyst introduction region 失效
标题翻译：使用催化剂引入区域制造半导体器件的方法
公开(公告)号：US5696003A
公开(公告)日：1997-12-09
申请号：US357648
申请日：1994-12-16
申请人： Naoki Makita , Takashi Funai , Yoshitaka Yamamoto , Yasuhiro Mitani , Katsumi Nomura , Tadayoshi Miyamoto , Takamasa Kosai
发明人： Naoki Makita , Takashi Funai , Yoshitaka Yamamoto , Yasuhiro Mitani , Katsumi Nomura , Tadayoshi Miyamoto , Takamasa Kosai
IPC分类号： H01L21/20 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12
CPC分类号： H01L21/2022 , H01L27/1277 , H01L29/66757 , Y10S148/016
摘要： Into an amorphous silicon film, catalyst elements for accelerating the crystallization are introduced. After patterning the amorphous silicon films in which the catalyst elements have been introduced into an island pattern, a heat treatment for the crystallization is conducted. Thus, the introduced catalyst elements efficiently diffuse only inside the island-patterned amorphous silicon films. As a result, a high-quality crystalline silicon film, having the crystal growth direction aligned in one direction and having no grain boundaries, is obtained. Using the thus formed crystalline silicon film, semiconductor devices having a high performance and stable characteristics are fabricated efficiently over the entire substrate, irrespective of the size of the devices.
摘要翻译：引入非晶硅膜，用于加速结晶的催化剂元素。在将催化剂元素引入岛状图案的非晶硅膜图案化之后，进行结晶化的热处理。因此，引入的催化剂元件仅在岛状图案化的非晶硅膜的内部有效地扩散。结果，获得了晶体生长方向在一个方向上排列并且不具有晶界的高质量晶体硅膜。使用如此形成的晶体硅膜，无论器件尺寸如何，都能在整个基板上有效地制造具有高性能和稳定特性的半导体器件。

15. 发明申请

US20130188110A1 THIN FILM TRANSISTOR SUBSTRATE, METHOD FOR PRODUCING THE SAME, AND DISPLAY DEVICE 有权
标题翻译：薄膜晶体管基板，其制造方法和显示装置
公开(公告)号：US20130188110A1
公开(公告)日：2013-07-25
申请号：US13821304
申请日：2011-09-02
申请人： Tadayoshi Miyamoto
发明人： Tadayoshi Miyamoto
IPC分类号： H01L29/786 , G02F1/136 , H01L29/66
CPC分类号： H01L29/7869 , G02F1/136 , H01L27/1225 , H01L27/1251 , H01L29/66742 , H01L29/78645 , H01L29/78648
摘要： An active matrix substrate (20a) includes: an insulating substrate (10a); a first thin film transistor (5a) including a first gate electrode (11b) located on the insulating substrate (10a) and a first oxide semiconductor layer (13a) having a first channel region (Ca); a second oxide semiconductor layer (13b) including a second gate electrode (11c) located on the insulating substrate (10a) and having a second channel region (Cb); a second gate insulating film (17) covering the first oxide semiconductor layer (13a) and the second semiconductor layer (13b); and a third gate electrode (25) located on the second gate insulating film (17) and facing the first channel region (Ca) and the second channel region (Cb) with the second gate insulating film (17) interposed therebetween.
摘要翻译：有源矩阵基板（20a）包括：绝缘基板（10a）; 包括位于所述绝缘基板（10a）上的第一栅电极（11b）和具有第一沟道区（Ca）的第一氧化物半导体层（13a）的第一薄膜晶体管（5a）第二氧化物半导体层（13b），其包括位于绝缘基板（10a）上并具有第二沟道区域（Cb）的第二栅电极（11c）; 覆盖第一氧化物半导体层（13a）和第二半导体层（13b）的第二栅极绝缘膜（17）; 以及位于第二栅极绝缘膜（17）上且与第二栅极绝缘膜（17）相对的第三沟道区（Ca）和第二沟道区（Cb）的第三栅电极（25）。

16. 发明申请

US20100072493A1 ACTIVE MATRIX SUBSTRATE 有权
标题翻译：主动矩阵基板
公开(公告)号：US20100072493A1
公开(公告)日：2010-03-25
申请号：US12442870
申请日：2007-09-25
申请人： Tadayoshi Miyamoto , Mitsuhiro Tanaka
发明人： Tadayoshi Miyamoto , Mitsuhiro Tanaka
IPC分类号： H01L33/00 , H01L21/8232
CPC分类号： H01L27/124 , G02F1/136204
摘要： In an active matrix substrate (100) of the present invention, a gate bus line (105) and a gate electrode (166) extend in the first direction (the x direction). At a contact portion (168) for electrically connecting the gate bus line (105) with the drain regions of a first-conductivity-type transistor section (162) and a second-conductivity-type transistor section (164), the direction of the straight line (L1) of the shortest distance (d1) between one of a plurality of first-conductivity-type drain connecting portions (168c) that is closest to the gate bus line (105) and the gate bus line (105) is inclined with respect to the second direction (the y direction).
摘要翻译：在本发明的有源矩阵基板（100）中，栅极总线（105）和栅电极（166）沿第一方向（x方向）延伸。在用于将栅极总线（105）与第一导电型晶体管部分（162）和第二导电型晶体管部分（164）的漏极区域电连接的接触部分（168）处，与栅极总线（105）最接近的多个第一导电型漏极连接部（168c）中的一个与栅极总线（105）之间的最短距离（d1）的直线（L1）倾斜相对于第二方向（y方向）。

17. 发明授权

US5966193A LCD device having coupling capacitances and shielding films 失效
标题翻译： LCD装置具有耦合电容和屏蔽膜
公开(公告)号：US5966193A
公开(公告)日：1999-10-12
申请号：US891697
申请日：1997-07-11
申请人： Hongyong Zhang , Akira Takenouchi , Tadayoshi Miyamoto , Atsushi Yoshinouchi
发明人： Hongyong Zhang , Akira Takenouchi , Tadayoshi Miyamoto , Atsushi Yoshinouchi
IPC分类号： G02F1/1343 , G02F1/136 , G02F1/1362 , G02F1/1368 , H01L29/786 , G02F1/1333
CPC分类号： G02F1/136209 , H01L27/1255
摘要： This invention is characterized by providing light shield patterning on a TFT substrate for an active matrix type liquid crystal display device. A liquid crystal display device comprising an active matrix circuit using a TFT having a top gate-type structure. The light-shield film are formed under a semiconductor layer and superposed at least one of the source bus line and the gate bus line. A capacitance is formed by the light-shield film and at least a part of the semiconductor layer with an insulating layer interposed therebetween.
摘要翻译：本发明的特征在于在有源矩阵型液晶显示装置的TFT基板上设置遮光图案。一种液晶显示装置，包括使用具有顶栅型结构的TFT的有源矩阵电路。遮光膜形成在半导体层之下，并且叠加在源极总线和栅极总线中的至少一个上。电容由遮光膜形成，半导体层的至少一部分隔着绝缘层形成。

18. 发明授权

US5821562A Semiconductor device formed within asymetrically-shaped seed crystal region 失效
标题翻译：在非对称形状的晶种区域内形成的半导体器件
公开(公告)号：US5821562A
公开(公告)日：1998-10-13
申请号：US452693
申请日：1995-05-30
申请人： Naoki Makita , Takashi Funai , Yoshitaka Yamamoto , Yasuhiro Mitani , Katsumi Nomura , Tadayoshi Miyamoto , Takamasa Kosai
发明人： Naoki Makita , Takashi Funai , Yoshitaka Yamamoto , Yasuhiro Mitani , Katsumi Nomura , Tadayoshi Miyamoto , Takamasa Kosai
IPC分类号： H01L21/20 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/786 , H01L29/04 , H01L29/06 , H01L31/036
CPC分类号： H01L21/2022 , H01L27/1277 , H01L29/66757 , Y10S148/016
摘要： Into an amorphous silicon film, catalyst elements for accelerating the crystallization are introduced. After patterning the amorphous silicon films in which the catalyst elements have been introduced into an island pattern, a heat treatment for the crystallization is conducted. Thus, the introduced catalyst elements efficiently diffuse only inside the island-patterned amorphous silicon films. As a result, a high-quality crystalline silicon film, having the crystal growth direction aligned in one direction and having no grain boundaries, is obtained. Using the thus formed crystalline silicon film, semiconductor devices having a high performance and stable characteristics are fabricated efficiently over the entire substrate, irrespective of the size of the devices.
摘要翻译：引入非晶硅膜，用于加速结晶的催化剂元素。在将催化剂元素引入岛状图案的非晶硅膜图案化之后，进行结晶化的热处理。因此，引入的催化剂元件仅在岛状图案化的非晶硅膜的内部有效地扩散。结果，获得了晶体生长方向在一个方向上排列并且不具有晶界的高质量晶体硅膜。使用如此形成的晶体硅膜，无论器件尺寸如何，都能在整个基板上有效地制造具有高性能和稳定特性的半导体器件。

19. 发明申请

US20140048812A1 SEMICONDUCTOR DEVICE, ACTIVE MATRIX BOARD, AND DISPLAY DEVICE 有权
标题翻译：半导体器件，有源矩阵板和显示器件
公开(公告)号：US20140048812A1
公开(公告)日：2014-02-20
申请号：US14113289
申请日：2012-04-20
申请人： Fumiki Nakano , Tadayoshi Miyamoto
发明人： Fumiki Nakano , Tadayoshi Miyamoto
IPC分类号： H01L27/12
CPC分类号： H01L27/1255 , G02F1/136209 , G09G3/3208 , G09G3/3648 , G09G2300/0814 , G09G2300/0852 , G09G2300/0876 , G09G2310/0259 , G09G2310/066 , G09G2320/0214 , G09G2320/041 , G09G2340/0435 , G09G2360/144 , H01L27/326 , H01L27/3272 , H01L29/78633 , H01L29/78648 , H04N1/00
摘要： Provided is a semiconductor device equipped with: a plurality of switching elements (T1, T2) that are connected in series; a first capacitance (Cs1) having one electrode connected to an end of the plurality of switching elements (T1, T2) and another electrode being connected to a first capacitance wiring line (CSL1); a second capacitance (Cs2) with one electrode connected to a node that connects two adjacent switching elements (T1, T2) among the plurality of switching elements, and another electrode being connected to a second capacitance wiring line (CSL2); and a light-shielding film that block light from being incident on at least one of the plurality of switching elements (T1, T2).
摘要翻译：本发明提供一种配备有串联连接的多个开关元件（T1，T2）的半导体器件。具有与多个开关元件（T1，T2）的端部连接的一个电极和与第一电容配线（CSL1）连接的另一个电极的第一电容（Cs1）。第二电容（Cs2），其中一个电极连接到连接多个开关元件中的两个相邻开关元件（T1，T2）的节点，另一个电极连接到第二电容布线（CSL2）; 以及阻挡光入射到多个开关元件（T1，T2）中的至少一个的遮光膜。

20. 发明授权

US08093601B2 Active matrix substrate 有权
标题翻译：有源矩阵基板
公开(公告)号：US08093601B2
公开(公告)日：2012-01-10
申请号：US12442870
申请日：2007-09-25
申请人： Tadayoshi Miyamoto , Mitsuhiro Tanaka
发明人： Tadayoshi Miyamoto , Mitsuhiro Tanaka
IPC分类号： H01L31/00 , H01L29/04
CPC分类号： H01L27/124 , G02F1/136204
摘要： In an active matrix substrate (100) of the present invention, a gate bus line (105) and a gate electrode (166) extend in the first direction (the x direction). At a contact portion (168) for electrically connecting the gate bus line (105) with the drain regions of a first-conductivity-type transistor section (162) and a second-conductivity-type transistor section (164), the direction of the straight line (L1) of the shortest distance (d1) between one of a plurality of first-conductivity-type drain connecting portions (168c) that is closest to the gate bus line (105) and the gate bus line (105) is inclined with respect to the second direction (the y direction).
摘要翻译：在本发明的有源矩阵基板（100）中，栅极总线（105）和栅电极（166）沿第一方向（x方向）延伸。在用于将栅极总线（105）与第一导电型晶体管部分（162）和第二导电型晶体管部分（164）的漏极区域电连接的接触部分（168）处，与栅极总线（105）最接近的多个第一导电型漏极连接部（168c）中的一个与栅极总线（105）之间的最短距离（d1）的直线（L1）倾斜相对于第二方向（y方向）。

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