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11. 发明授权

US07441101B1 Thread-aware instruction fetching in a multithreaded embedded processor 有权
标题翻译：线程感知指令在多线程嵌入式处理器中获取
公开(公告)号：US07441101B1
公开(公告)日：2008-10-21
申请号：US10773385
申请日：2004-02-05
申请人： Donald E. Steiss , Earl T Cohen , John J Williams, Jr.
发明人： Donald E. Steiss , Earl T Cohen , John J Williams, Jr.
IPC分类号： G06F9/312 , G06F9/48
CPC分类号： G06F9/3851 , G06F9/3802
摘要： The present invention provides a multithreaded processor, such as a network processor, that fetches instructions in a pipeline stage based on feedback signals from later stages. The multithreaded processor comprises a pipeline with an instruction unit in the early stage and an instruction queue, a thread interleaver, and an execution pipeline in the later stages. Feedback signals from the later stages cause the instruction unit to block fetching, immediately fetch, raise priority, or lower priority for a particular thread. The instruction queue generates a queue signal, on a per thread basis, responsive to a thread queue condition, etc., the thread interleaver generates an interleaver signal responsive to a thread condition, etc., and the execution pipeline generates an execution signal responsive to an execution stall, etc.
摘要翻译：本发明提供了一种多线程处理器，例如网络处理器，其基于来自后期阶段的反馈信号在流水线级中取指令。多线程处理器包括在早期阶段具有指令单元的流水线以及稍后阶段中的指令队列，线程交织器和执行流水线。来自后期的反馈信号导致指令单元阻止特定线程的取出，立即获取，提高优先级或降低优先级。指令队列响应于线程队列条件等而在每个线程的基础上生成队列信号，线程交织器响应于线程状态等产生交织器信号，并且执行流水线生成响应于执行档等

12. 发明授权

US06567906B2 Secure computing device including virtual memory table look-aside buffer with non-relocatable page of memory 有权
标题翻译：安全计算设备包括具有不可重定位页面的内存的虚拟内存表查看缓冲区
公开(公告)号：US06567906B2
公开(公告)日：2003-05-20
申请号：US09827851
申请日：2001-04-06
申请人： Frank L. Laczko, Sr. , Donald E. Steiss
发明人： Frank L. Laczko, Sr. , Donald E. Steiss
IPC分类号： G06F1200
CPC分类号： G06F21/64 , G06F12/145 , G06F21/51 , G06F21/575 , G06F2207/7219 , G06F2211/008 , G06F2211/1097
摘要： A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic program is loaded and checks the program at the predetermined physical address against a standard. The diagnostic program then indicates that the program is verified as secure if it meets the standard or non-verified as secure if it does not meet the standard. If the program is not verified as secure, then the diagnostic program may take remedial action such as disabling normal operation of the program, be transmitting a predetermined message via the system modem or downloading another copy of the program via the modem. The program is made non-relocatable using a special table look-aside buffer having a fixed virtual address register and a corresponding fixed physical address register.
摘要翻译：诊断程序可以检查程序的安全性。程序存储在存储器中预定的不可重定位的物理地址。加载诊断程序并按照标准检查预定物理地址的程序。然后，诊断程序指示如果程序符合标准或未验证为安全（如果不符合标准），则该程序被证实为安全的。如果程序未被证实为安全的，则诊断程序可以采取补救措施，例如禁用程序的正常操作，通过系统调制解调器发送预定的消息，或通过调制解调器下载程序的另一个副本。使用具有固定虚拟地址寄存器和对应的固定物理地址寄存器的特殊表格后备缓冲器使该程序不可重定位。

13. 发明授权

US06405351B1 System for verifying leaf-cell circuit properties 有权
标题翻译：验证叶电路电路性能的系统
公开(公告)号：US06405351B1
公开(公告)日：2002-06-11
申请号：US09603708
申请日：2000-06-27
申请人： Donald E. Steiss , Anthony M. Hill , Richard P. Wiley
发明人： Donald E. Steiss , Anthony M. Hill , Richard P. Wiley
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A computer system (10). The computer system comprises processing circuitry (14) and storage circuitry (24) for storing a plurality of files. The plurality of files include a circuit description file (243) comprising data describing devices and signals in a circuit. The plurality of files also include a plurality of list expressions (244) relating to one of devices, signals, or devices and signals described by the data in the circuit description. Still further, the plurality of files also include a plurality of rules (245). The processing circuitry is programmed to perform various steps. These steps include processing (34) the plurality of list expressions to extract a plurality of lists in response to the circuit description. Each of the plurality of lists comprises a non-negative integer number of elements. The programmed steps further include processing (38) the plurality of rules to evaluate one or more of the plurality of lists to verify connection accuracy within the circuit in response to the non-negative integer number of elements.
摘要翻译：计算机系统（10）。计算机系统包括用于存储多个文件的处理电路（14）和存储电路（24）。多个文件包括电路描述文件（243），其包括描述电路中的装置和信号的数据。多个文件还包括与电路描述中的数据描述的设备，信号或设备之一相关的多个列表表达式（244）。此外，多个文件还包括多个规则（245）。处理电路被编程以执行各种步骤。这些步骤包括响应于电路描述处理（34）多个列表表达式以提取多个列表。多个列表中的每一个包括非负整数个元素。所编程的步骤还包括处理（38）多个规则以评估多个列表中的一个或多个，以便响应于非负整数元素来验证电路内的连接精度。

14. 发明授权

US06385120B1 Power-off state storage apparatus and method 有权
标题翻译：断电状态存储装置和方法
公开(公告)号：US06385120B1
公开(公告)日：2002-05-07
申请号：US09998783
申请日：2001-12-03
申请人： Donald E. Steiss
发明人： Donald E. Steiss
IPC分类号： G11C720
CPC分类号： G11C14/00
摘要： A circuit for power-off state storage in an electronic device having a positive power supply includes a storage circuit comprising first and second storage capacitors and a write circuit having a plurality of N-type transistors coupled to the storage circuit. The write circuit is operable to write a data bit to the first and second storage capacitors. The power-off state storage circuit also has a sense amplifier connected to the storage circuit and that is operable to read the data bit stored by the storage capacitors. The first and second capacitors in the storage circuit are electrically isolated from the positive power supply such that when the positive power supply is terminated any charge stored on the first and second capacitors is prevented from discharging to the terminated power supply.
摘要翻译：一种具有正电源的电子设备中的断电状态存储电路包括：包括第一和第二存储电容器的存储电路和具有耦合到存储电路的多个N型晶体管的写入电路。写入电路可操作以将数据位写入第一和第二存储电容器。断电状态存储电路还具有连接到存储电路的读出放大器，并且可操作以读取由存储电容器存储的数据位。存储电路中的第一和第二电容器与正电源电隔离，使得当正电源终止时，防止存储在第一和第二电容器上的电荷向终端电源放电。

15. 发明授权

US09176739B2 System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions 有权
标题翻译：用于检查顺序和非顺序取指令的运行时一致性的系统和方法
公开(公告)号：US09176739B2
公开(公告)日：2015-11-03
申请号：US13204346
申请日：2011-08-05
申请人： Donald E. Steiss
发明人： Donald E. Steiss
IPC分类号： G06F21/54 , G06F21/12 , G06F11/10 , G06F9/32 , G06F21/52 , G06F9/30 , G06F9/38
CPC分类号： G06F9/322 , G06F9/30185 , G06F9/3861 , G06F11/10 , G06F21/125 , G06F21/52
摘要： A system and method includes modules for determining whether an instruction is a target of a non-sequential fetch operation with an expected numerical property value, and avoiding execution of the instruction if it is the target of the non-sequential fetch operation and does not have the expected numerical property. Other embodiments include encoding an instruction with a functionality that is a target of a non-sequential fetch operation with an expected numerical property value. Instructions with the same functionality that are not targets of non-sequential fetch operations can be encoded with a different numerical property value. More specific embodiments can include a numerical property of parity, determining whether the instruction is valid, and throwing an exception, setting status bits, sending an interrupt to a control processor, and a combination thereof to avoid execution.
摘要翻译：一种系统和方法包括用于确定指令是否是具有预期数值属性值的非顺序取出操作的目标的模块，并且如果指令是非顺序取出操作的目标并且不具有预期的数值属性。其他实施例包括用具有预期数值属性值的具有作为非顺序取出操作的目标的功能的指令进行编码。具有不是非顺序提取操作的目标的相同功能的指令可以使用不同的数值属性值进行编码。更具体的实施例可以包括奇偶性的数值属性，确定指令是否有效，以及抛出异常，设置状态位，向控制处理器发送中断及其组合以避免执行。

16. 发明申请

US20130036294A1 SYSTEM AND METHOD FOR INSTRUCTION SETS WITH RUN-TIME CONSISTENCY CHECK 有权
标题翻译：具有运行时间一致性检查的指令集的系统和方法
公开(公告)号：US20130036294A1
公开(公告)日：2013-02-07
申请号：US13204346
申请日：2011-08-05
申请人： Donald E. Steiss
发明人： Donald E. Steiss
IPC分类号： G06F9/30
CPC分类号： G06F9/322 , G06F9/30185 , G06F9/3861 , G06F11/10 , G06F21/125 , G06F21/52
摘要： A system and method includes modules for determining whether an instruction is a target of a non-sequential fetch operation with an expected numerical property value, and avoiding execution of the instruction if it is the target of the non-sequential fetch operation and does not have the expected numerical property. Other embodiments include encoding an instruction with a functionality that is a target of a non-sequential fetch operation with an expected numerical property value. Instructions with the same functionality that are not targets of non-sequential fetch operations can be encoded with a different numerical property value. More specific embodiments can include a numerical property of parity, determining whether the instruction is valid, and throwing an exception, setting status bits, sending an interrupt to a control processor, and a combination thereof to avoid execution.
摘要翻译：一种系统和方法包括用于确定指令是否是具有预期数值属性值的非顺序取出操作的目标的模块，并且如果指令是非顺序取出操作的目标并且不具有预期的数值属性。其他实施例包括用具有预期数值属性值的具有作为非顺序取出操作的目标的功能的指令进行编码。具有不是非顺序提取操作的目标的相同功能的指令可以使用不同的数值属性值进行编码。更具体的实施例可以包括奇偶性的数值属性，确定指令是否有效，以及抛出异常，设置状态位，向控制处理器发送中断及其组合以避免执行。

17. 发明授权

US06895493B2 System and method for processing data in an integrated circuit environment 有权
标题翻译：用于在集成电路环境中处理数据的系统和方法
公开(公告)号：US06895493B2
公开(公告)日：2005-05-17
申请号：US10206420
申请日：2002-07-25
申请人： Donald E. Steiss , Zheng Zhu
发明人： Donald E. Steiss , Zheng Zhu
IPC分类号： G06F9/345 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3824 , G06F9/345 , G06F9/3834
摘要： A method for processing data is provided that includes storing a write operation in a store buffer that indicates a first data element is to be written to a memory array element. The write operation includes a first address associated with a location in the memory array element to where the first data element is to be written. A read operation may be received at the store buffer, indicating that a second data element is to be read from the memory array element. The read operation includes a second address associated with a location in the memory array element from where the second data element is to be read. A hashing operation may be executed on the first and second addresses such that first and second hashed addresses are respectively produced. The hashed addresses are compared. If they match, the first data element is written to the memory array element before the read operation is executed.
摘要翻译：提供了一种用于处理数据的方法，包括将写入操作存储在指示要写入存储器阵列元件的第一数据元素的存储缓冲器中。写入操作包括与存储器阵列元件中要被写入第一数据元素的位置相关联的第一地址。可以在存储缓冲器处接收读取操作，指示要从存储器阵列元件读取第二数据元素。读取操作包括与存储器阵列元件中要从其读取第二数据元素的位置相关联的第二地址。可以在第一和第二地址上执行散列操作，使得分别产生第一和第二散列地址。比较散列地址。如果它们匹配，则在执行读取操作之前，将第一数据元素写入存储器阵列元件。

18. 发明授权

US06571363B1 Single event upset tolerant microprocessor architecture 有权
标题翻译：单事件容忍微处理器架构
公开(公告)号：US06571363B1
公开(公告)日：2003-05-27
申请号：US09464635
申请日：1999-12-15
申请人： Donald E. Steiss
发明人： Donald E. Steiss
IPC分类号： G06F1127
CPC分类号： G06F11/1497 , G06F2201/83
摘要： A single-event-upset, fault-tolerant data processor architecture enables error detection and correction according to algorithms given. A hardware intensive solution compares signatures of two passes through a block of instructions. A match of signatures generated from the two passes through the block of instructions indicates valid operations, a mismatch indicates an error. A software assisted solution compares a signature generated from one pass through a block of instructions with a signature pre-calculated by a compiler or with a one of a set of pre-calculated signature selected at run time. This is useful for digital signal processor design using deep-sub-micron devices and dynamic logic for superior system performance by enabling detection of errors that can result from the low noise-immunity in circuits using higher impedance smaller devices with low threshold voltage and dynamic logic.
摘要翻译：单事件不安，容错数据处理器架构可以根据给出的算法进行错误检测和校正。硬件密集型解决方案通过一组指令比较两次通过的签名。通过指令块生成的两个签名的匹配表示有效的操作，不匹配表示错误。软件辅助解决方案将从一个通过一个指令生成的签名与由编译器预先计算的签名或在运行时选择的一组预先计算的签名中的一个进行比较。这对使用深亚微米器件和动态逻辑的数字信号处理器设计非常有用，可以通过使用低阈值电压和动态逻辑的较高阻抗较小器件的电路中的低噪声抗扰度来检测错误，从而获得卓越的系统性能。

19. 发明授权

US06266754B1 Secure computing device including operating system stored in non-relocatable page of memory 有权
标题翻译：安全计算设备，包括存储在不可重定位的存储器页面中的操作系统
公开(公告)号：US06266754B1
公开(公告)日：2001-07-24
申请号：US09314397
申请日：1999-05-19
申请人： Frank L. Laczko, Sr. , Donald E. Steiss
发明人： Frank L. Laczko, Sr. , Donald E. Steiss
IPC分类号： G06F1210
CPC分类号： G06F21/64 , G06F12/145 , G06F21/51 , G06F21/575 , G06F2207/7219 , G06F2211/008 , G06F2211/1097
摘要： A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic program is loaded and checks the program at the predetermined physical address against a standard. The diagnostic program then indicates that the program is verified as secure if it meets the standard or non-verified as secure if it does not meet the standard. If the program is not verified as secure, then the diagnostic program may take remedial action such as disabling normal operation of the program, be transmitting a predetermined message via the system modem or downloading another copy of the program via the modem. The program is made non-relocatable using a special table look-aside buffer having a fixed virtual address register and a corresponding fixed physical address register.
摘要翻译：诊断程序可以检查程序的安全性。程序存储在存储器中预定的不可重定位的物理地址。加载诊断程序并按照标准检查预定物理地址的程序。然后，诊断程序指示如果程序符合标准或未验证为安全（如果不符合标准），则该程序被证实为安全的。如果程序没有被证实为安全的，则诊断程序可以采取补救措施，例如禁用程序的正常操作，通过系统调制解调器发送预定的消息，或通过调制解调器下载程序的另一副本。使用具有固定虚拟地址寄存器和对应的固定物理地址寄存器的特殊表格后备缓冲器使该程序不可重定位。

20. 发明授权

US6061811A Circuits, systems, and methods for external evaluation of microprocessor built-in self-test 失效
标题翻译：微处理器内置自检外部评估的电路，系统和方法
公开(公告)号：US6061811A
公开(公告)日：2000-05-09
申请号：US961788
申请日：1997-10-31
申请人： James O. Bondi , Joel J. Graber , Donald E. Steiss , John M. Johnsen
发明人： James O. Bondi , Joel J. Graber , Donald E. Steiss , John M. Johnsen
IPC分类号： G06F11/267 , G06F11/00
CPC分类号： G06F11/2236
摘要： A microprocessor (10) operating in response to a clock signal (CLK) having a clock period. The microprocessor includes a readable memory (16), and this readable memory stores code (BIST) for performing diagnostic evaluations of the microprocessor. The diagnostic evaluations include a first evaluation to occur under non-failure operation at a first clock period (24) and a last evaluation to occur under non-failure operation at a last clock period (26). The microprocessor further includes circuitry (14) for issuing a series of addresses to the readable memory in order to address the code for performing diagnostic evaluations of the microprocessor. Still further, the microprocessor includes a conductor (D0) externally accessible and for providing a signal from the microprocessor. Lastly, the microprocessor includes circuitry (12) for outputting a diagnostic signal on the externally accessible conductor during performance of the diagnostic evaluations. Given the externally accessible conductor, divergence of the diagnostic signal from a predetermined pattern before the last dock period indicates a failure of the diagnostic evaluations before the last clock period.
摘要翻译：响应于具有时钟周期的时钟信号（CLK）工作的微处理器（10）。微处理器包括可读存储器（16），并且该可读存储器存储用于执行微处理器的诊断评估的代码（BIST）。诊断评估包括在第一时钟周期（24）的非故障操作下进行的第一评估，以及在最后时钟周期（26）的非故障操作下发生的最后评估。微处理器还包括用于向可读存储器发出一系列地址以便寻址用于执行微处理器的诊断评估的代码的电路（14）。此外，微处理器包括外部可访问的导体（D0），用于提供来自微处理器的信号。最后，微处理器包括用于在执行诊断评估期间在外部可访问的导体上输出诊断信号的电路（12）。给定外部可访问的导体，诊断信号在最后一个停靠期之前的预定模式的发散指示在最后时钟周期之前的诊断评估失败。

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