专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07046685B1 Scheduling control system and switch 失效
标题翻译：调度控制系统和开关
公开(公告)号：US07046685B1
公开(公告)日：2006-05-16
申请号：US09460898
申请日：1999-12-14
申请人： Naoki Matsuoka , Kenichi Kawarai , Hiroshi Tomonaga , Tsuguo Kato
发明人： Naoki Matsuoka , Kenichi Kawarai , Hiroshi Tomonaga , Tsuguo Kato
IPC分类号： H04L12/56 , H04L12/54 , H04L12/43 , H04J7/00
CPC分类号： H04L49/1553 , H04L12/5601 , H04L41/0896 , H04L47/50 , H04L47/6225 , H04L49/3045 , H04L2012/5679 , H04L2012/5681
摘要： A scheduling system is capable of causing no deterioration of characteristics even under equal and unequal loads, eliminating the necessity for high-speed repetitive scheduling and complicated arithmetic processes, simplifying its architecture and having its processing speed which does not depend upon a device capability. For attaining this system, an inter-highway pointer is updated to an adjacent line (rightward) when the scheduling for all the lines are finished. If the inter-highway pointer is updated N-times in the same direction (clockwise), the same pointer is updated to an adjacent line in a reverse direction (counterclockwise) in next N-processes of scheduling.
摘要翻译：调度系统即使在相等和不相等的负载下也不会导致特性恶化，消除了高速重复调度和复杂运算过程的必要性，简化了其架构并且具有不依赖于设备能力的处理速度。为了实现该系统，当所有行的调度完成时，将将公路间指针更新为相邻行（向右）。如果公路间指针以相同方向（顺时针）N次更新，则在下一个N个调度处理中，相同的指针在相反方向（逆时针）更新为相邻的行。

12. 发明授权

US07016366B2 Packet switch that converts variable length packets to fixed length packets and uses fewer QOS categories in the input queues that in the outout queues 失效
标题翻译：分组交换机，将可变长度数据包转换为固定长度数据包，并在输出队列中使用较少的QOS类别
公开(公告)号：US07016366B2
公开(公告)日：2006-03-21
申请号：US09813226
申请日：2001-03-20
申请人： Kenichi Kawarai , Hiroshi Tomonaga , Naoki Matsuoka , Tsuguo Kato
发明人： Kenichi Kawarai , Hiroshi Tomonaga , Naoki Matsuoka , Tsuguo Kato
IPC分类号： H04L12/28
CPC分类号： H04L49/30 , H04L47/10 , H04L47/15 , H04L47/20 , H04L47/2433 , H04L47/2441 , H04L47/29 , H04L47/30 , H04L47/32 , H04L47/50 , H04L47/60 , H04L47/627 , H04L49/101 , H04L49/201 , H04L49/205 , H04L49/254 , H04L49/3009 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/3081 , H04L49/503 , H04L49/608 , H04L2012/5647 , H04L2012/5651 , H04L2012/5652 , H04L2012/5679 , H04L2012/5682
摘要： To achieve QoS control, drop control and multicast control of a variable-length packet at high speed in small scale hardware, a packet divider divides a variable-length packet into fixed-length packets, and an input buffer section stores the divided fixed-length packets into queues by output lines and by QoS classes. A large number of QoS classes are mapped into only two kinds of classes including a guaranteed bandwidth class for which an assigned bandwidth is guaranteed and a best effort class for which a surplus bandwidth is allocated, thereby to achieve scheduling at the input side by an inter-line scheduler. An output buffer section assembles a variable-length packet from fixed-length packets that have been obtained by switching at a switch section in an output buffer section. A QoS control is performed based on a packet length.
摘要翻译：为了在小规模硬件中高速实现可变长度分组的QoS控制，丢弃控制和组播控制，分组分配器将可变长度分组分成固定长度分组，并且输入缓冲部分存储分割的固定长度数据包通过输出行和QoS类进入队列。大量的QoS等级被映射到只有两种类型，包括保证分配的带宽的保证带宽等级，以及为其分配剩余带宽的最佳努力类，从而通过一个inter 线程调度器输出缓冲器部分通过在输出缓冲器部分中的切换部分处切换而获得的固定长度分组组装可变长度分组。基于分组长度执行QoS控制。

13. 发明授权

US06411620B1 Connectionless communication system 失效
标题翻译：无连接通信系统
公开(公告)号：US06411620B1
公开(公告)日：2002-06-25
申请号：US08970825
申请日：1997-11-14
申请人： Tadahiro Takase , Kazuo Hajikano , Takeshi Kawasaki , Toshio Shimoe , Tetsuo Tachibana , Teruaki Hagihara , Satoshi Kakuma , Masami Murayama , Ryuichi Takechi , Satoshi Kuroyanagi , Jyoei Kamoi , Hiroshi Tomonaga
发明人： Tadahiro Takase , Kazuo Hajikano , Takeshi Kawasaki , Toshio Shimoe , Tetsuo Tachibana , Teruaki Hagihara , Satoshi Kakuma , Masami Murayama , Ryuichi Takechi , Satoshi Kuroyanagi , Jyoei Kamoi , Hiroshi Tomonaga
IPC分类号： H04L1228
CPC分类号： H04L12/5602 , H04L2012/5616 , H04L2012/562 , H04L2012/5627 , H04L2012/563 , H04L2012/5645 , H04L2012/5652 , H04Q11/0478
摘要： The object of the present invention is accomodating local connectionless information (data that is immediately transferred without establishing a path to a receive side), such as LAN data in a local area network, by an asynchronous transfer mode (ATM) network using a connection-oriented communication system (which makes data transfers after verifying that a path to the receive side has been established), thereby performing efficient, fast routing of connectionless information. A connectionless communication system of the present invention is equipped with connectionless information cell assembly/deassembly means for bi-directional conversion between variable-length connectionless information and fixed-length connectionless cells, routing control means for analyzing a destination address of information in connectionless cells and controlling the routing of the connectionless cells; and an ATM network for connecting the connectionless information cell assembly/deassembly means and the routing control means by a permanent virtual channel serving as a fixed path and connecting the routing control means together by a virtual channel serving as a semi-fixed path, whereby connectionless information is segmented into connectionless cells and the connectionless information is exchanged within the ATM network in connectionless cell units.
摘要翻译：本发明的目的是通过异步传输模式（ATM）网络使用本地无连接信息（即，在不建立到接收侧的路径的情况下立即传送的数据），诸如局域网中的LAN数据，（在验证到接收侧的路径已经建立之后进行数据传输），从而执行无连接信息的有效，快速的路由。本发明的无连接通信系统配备有用于在可变长度无连接信息和固定长度无连接小区之间进行双向转换的无连接信息单元组合/拆卸装置，用于分析无连接小区中的信息的目的地地址的路由控制装置，以及控制无连接单元的路由; 以及用于通过用作固定路径的永久虚拟通道连接无连接信息单元组装/拆卸装置和路由控制装置并通过用作半固定路径的虚拟通道将路由控制装置连接在一起的ATM网络，由此无连接信息被分割成无连接小区，并且在无连接小区单元内的ATM网络内交换无连接信息。

14. 发明授权

US08432925B2 Apparatus and method for controlling buffering of an arrival packet 有权
标题翻译：用于控制到达分组的缓冲的装置和方法
公开(公告)号：US08432925B2
公开(公告)日：2013-04-30
申请号：US12404502
申请日：2009-03-16
申请人： Kazuto Nishimura , Hiroshi Tomonaga , Akihiro Hata , Masamichi Kasa
发明人： Kazuto Nishimura , Hiroshi Tomonaga , Akihiro Hata , Masamichi Kasa
IPC分类号： H04L12/56
CPC分类号： H04L47/283 , H04L47/10 , H04L47/32 , H04L49/505
摘要： An apparatus for controlling buffering of an arrival packet. The apparatus includes a packet buffer for temporarily storing each of one or more packets to be transmitted in association with an arrival time thereof, and a packet discard section for determining an arrival packet to be discarded or to be stored in the packet buffer, based on a discard condition defined by using a packet residence time that is calculated on the basis of one or more residence times of one or more packets staying in the packet buffer, wherein the arrival packet is defined as a packet that has newly arrived at the apparatus.
摘要翻译：一种用于控制到达分组的缓冲的装置。该装置包括：分组缓冲器，用于临时存储与其到达时间相关联的要发送的一个或多个分组中的每一个;以及分组丢弃部分，用于基于丢弃或要存储在分组缓冲器中的到达分组，基于通过使用基于停留在分组缓冲器中的一个或多个分组的一个或多个停留时间计算的分组停留时间定义的丢弃条件，其中到达分组被定义为新到达该设备的分组。

15. 发明授权

US08306045B2 Packet forwarding apparatus and method for discarding packets 有权
标题翻译：用于丢弃分组的分组转发装置和方法
公开(公告)号：US08306045B2
公开(公告)日：2012-11-06
申请号：US12361655
申请日：2009-01-29
申请人： Akihiro Hata , Hiroshi Tomonaga , Katsumi Imamura
发明人： Akihiro Hata , Hiroshi Tomonaga , Katsumi Imamura
IPC分类号： G06F3/00 , G06F5/00 , H04L12/28 , H04L12/56
CPC分类号： H04L47/10 , H04L47/283 , H04L47/32 , H04L49/254 , H04L49/503 , H04L49/90 , H04L49/9047 , H04L49/9078
摘要： The packet forwarding apparatus of the present invention includes a packet buffer for temporarily storing packets to be forwarded, a timer for measuring the time of every predetermined unit period, a plurality of first queues corresponding to each of a plurality of address groups that form the packet buffer, a plurality of second queues that are provided corresponding to the property of the packets, a first controller for executing the writing of the packets, and a second controller for executing the discarding of the packets. According to this invention, through managing the first queues and the second queues, packets in the packet buffer can be discarded without the packets being read from the packet buffer.
摘要翻译：本发明的分组转发装置包括用于临时存储要转发的分组的分组缓冲器，用于测量每个预定单位周期的时间的定时器，对应于形成分组的多个地址组中的每一个的多个第一队列缓冲器，对应于分组的属性提供的多个第二队列，用于执行分组的写入的第一控制器，以及用于执行丢弃分组的第二控制器。根据本发明，通过管理第一队列和第二队列，可以丢弃分组缓冲器中的分组，而不从分组缓冲器读取分组。

16. 发明授权

US08937962B2 Packet buffering device and packet discarding method 有权
标题翻译：数据包缓存装置和数据包丢弃方法
公开(公告)号：US08937962B2
公开(公告)日：2015-01-20
申请号：US13195109
申请日：2011-08-01
申请人： Hiroshi Tomonaga , Kazuto Nishimura
发明人： Hiroshi Tomonaga , Kazuto Nishimura
IPC分类号： H04L12/801 , H04L12/853 , H04L12/841 , H04L12/835 , H04L12/823 , H04L29/06
CPC分类号： H04L47/10 , H04L47/2416 , H04L47/28 , H04L47/30 , H04L47/32 , H04L65/80
摘要： A packet buffering device includes: a queue for temporarily holding an arriving packet; a residence time predicting unit which predicts a length of time during which the arriving packet will reside in the queue; and a packet discarding unit which discards the arriving packet when the length of time predicted by the residence time predicting unit exceeds a first reference value.
摘要翻译：分组缓存装置包括：用于临时保持到达分组的队列; 停留时间预测单元，其预测到达的分组将驻留在队列中的时间长度; 以及分组丢弃单元，当由所述停留时间预测单元预测的时间长度超过第一参考值时，丢弃所述到达分组。

17. 发明授权

US08189589B2 Apparatus and method for forwarding packet data 有权
标题翻译：转发数据包数据的装置和方法
公开(公告)号：US08189589B2
公开(公告)日：2012-05-29
申请号：US12405393
申请日：2009-03-17
申请人： Jun Tanaka , Hiroshi Tomonaga , Takashi Kuwabara , Hiroshi Kurosaki
发明人： Jun Tanaka , Hiroshi Tomonaga , Takashi Kuwabara , Hiroshi Kurosaki
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/22 , H04L41/0659 , H04L45/28 , H04L49/254 , H04L49/3009 , H04L49/351 , H04L49/557
摘要： An apparatus includes an input part, a plurality of output parts, and a switching part. The input part inputs a packet and builds at least one forwarding data block including a predetermined destination identifier and packet data extracted from the inputted packet. The switching part includes a forwarding destination storing section for storing, in association with a predetermined destination identifier, a forwarding destination identifier identifying one of the plurality of output parts, and receives the at least one forwarding data block from the input part, and forwards it to one of the plurality of output parts on the basis of forwarding destination storing section which is updated in response to a change in the operating state of the plurality of output parts.
摘要翻译：一种装置包括输入部分，多个输出部分和切换部分。输入部分输入分组，构建至少一个转发数据块，该转发数据块包括预定的目的地标识符和从输入的分组提取的分组数据。切换部分包括转发目的地存储部分，用于与预定的目的地标识符相关联地存储识别多个输出部分之一的转发目的地标识符，并从输入部分接收至少一个转发数据块，并将其转发基于转发目的地存储部分，响应于多个输出部分的操作状态的改变来更新多个输出部分中的一个输出部分。

18. 发明授权

US07904677B2 Memory control device 有权
标题翻译：内存控制装置
公开(公告)号：US07904677B2
公开(公告)日：2011-03-08
申请号：US12230252
申请日：2008-08-26
申请人： Hidenori Sugai , Hiroshi Tomonaga , Satoshi Nemoto
发明人： Hidenori Sugai , Hiroshi Tomonaga , Satoshi Nemoto
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories.
摘要翻译：一种可以提高存储器接口速度的存储器控制装置。分组分解部分将分组数据分解成分段并检测分组质量信息。存储器管理部分具有地址管理表，并根据分组质量信息管理分组数据被存储的状态。分段/请求信息反汇编器通过访问单元将段分解成数据，通过该存取单元可以写入/读取存储器，并根据访问单元生成写入请求和读取请求。存储器访问控制器避免由于存储体约束而被禁止的存储体存取，从写入请求或所生成的读取请求中提取与可访问存储体相对应的写入请求或读取请求，并且获得对存储器的写入/读取访问。

19. 发明申请

US20100232291A1 DATA TRANSMISSION DEVICE 有权
标题翻译：数据传输设备
公开(公告)号：US20100232291A1
公开(公告)日：2010-09-16
申请号：US12783754
申请日：2010-05-20
申请人： Masaki Hirota , Hiroshi Tomonaga , Akihiro Hata , Shigeyuki Kobayashi
发明人： Masaki Hirota , Hiroshi Tomonaga , Akihiro Hata , Shigeyuki Kobayashi
IPC分类号： H04L12/24 , H04L12/56
CPC分类号： H04L47/125 , H04L49/1523 , H04L49/557
摘要： In a data transmission device and method provided with e.g. duplexed switches outputting frames in the order of input for continuing the communication without instantaneous interruptions even though one of the switches are faulted, input interfaces generate frames in which every time data is inputted, input order information indicating the input order is added to the data together with unique information of each input interface and providing the frame generated to the switches in parallel. At least one output interface sequentially stores the frames outputted from the switches for every unique information and selects a first arrived frame among the frames stored with same input order information.
摘要翻译：在具有例如数据传输设备和方法的数据传输设备和方法中，双工开关以输入顺序输出帧，以便即使其中一个开关发生故障，继续进行通信也不会发生瞬时中断，输入接口产生每次输入数据的帧，将表示输入顺序的输入顺序信息添加到数据中具有每个输入接口的独特信息，并且并行地向交换机提供生成的帧。至少一个输出接口对于每个唯一信息顺序地存储从开关输出的帧，并且选择在具有相同输入顺序信息存储的帧中的第一到达帧。

20. 发明申请

US20090296698A1 DATA SWITCHING METHOD AND CIRCUIT 审中-公开
标题翻译：数据切换方法与电路
公开(公告)号：US20090296698A1
公开(公告)日：2009-12-03
申请号：US12539762
申请日：2009-08-12
申请人： Mitsuru Sutou , Makoto Shimizu , Hiroshi Tomonaga
发明人： Mitsuru Sutou , Makoto Shimizu , Hiroshi Tomonaga
IPC分类号： H04L12/50
CPC分类号： H04L49/103 , H04L49/3027
摘要： For restricting a scale increase of a switch device using a shared buffer, segments are received at input ports with each phase being shifted and are each composed of a predetermined length data in which each data is connected in series by a predetermined number. The segments are written in shared buffers at the same address in sequence for each segment, where the shared buffers are provided in parallel by the predetermined number. The address for each output port set in each segment is stored each time the writing is performed and the stored address is referred to in the sequence for each output port thereby to read each predetermined length data based on the address referred to from each shared buffer. Each predetermined length data read is connected in series and outputted to each output port.
摘要翻译：为了限制使用共享缓冲器的开关装置的规模增加，在每个相位被移位的输入端口处接收段，并且每个都由预定长度数据组成，其中每个数据以预定数量串联连接。对于每个段，段被顺序地写在相同地址的共享缓冲器中，其中共享缓冲器并行提供预定数量。每次执行写入时存储每个输出端口的每个输出端口的地址，并且在每个输出端口的序列中参考存储的地址，从而基于每个共享缓冲器所参考的地址来读取每个预定长度的数据。每个预定长度的数据读取串联连接并输出到每个输出端口。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式