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    • 5. 发明授权
    • Procedure for switching-over systems
    • 切换系统的过程
    • US5488606A
    • 1996-01-30
    • US216149
    • 1994-03-21
    • Satoshi KakumaShuji YoshimuraKazuo HajikanoMasami MurayamaYuzo Okuyama
    • Satoshi KakumaShuji YoshimuraKazuo HajikanoMasami MurayamaYuzo Okuyama
    • H04Q3/00H04L12/70H04L29/14H04L12/56
    • H04L49/153H04L49/552H04L69/40H04L2012/5627H04L49/1523H04L49/30
    • An ATM (asynchronous transfer mode) exchange has a buffer for system #0 and a buffer for system #1 providing P-MEM's for storing data including an A bit and for a VCI/VPI currently in use is set to "1'. Upon detecting a switchover between the systems, every B bit is reset to "0". When the exchange while changing from a master to a slave receives a cell having a slave indication and while changing from a slave to a master it receives a cell having a master indication, respective systems rewrite B bits for VCI/VPI's of respective cells to "1". In the meantime, each of the P-MEM's calculates exclusive "OR" operations between the A bit and the B bit for every VCI/VPI, and further obtains a disjunction among all the exclusive "OR" operations thus obtained. Then, when both P-MEM's obtain "0" for their respective disjunctions, cells are read out from one of the buffers in the system changing from a slave to a master. This enables the ATM exchange having a switch duplexed by mutually asynchronous active and backup systems to switchover the systems without causing a cell to be duplicated or lost.
    • ATM(异步传输模式)交换机具有用于系统#0的缓冲器和用于系统#1的缓冲器,提供用于存储包括A位的数据的P-MEM,并且当前使用的VCI / VPI被设置为“1” 检测系统之间的切换,每个B位复位为“0”,当从主机切换到从机的交换机接收到具有从机指示的单元,并且在从从机更改为主机时,接收具有 主指示,相应的系统将各单元的VCI / VPI的B位重写为“1”,同时每个P-MEM针对每个VCI / VPI计算A位和B位之间的独占“或”运算, 并且在所得到的所有排他“OR”运算中进一步获得分离,然后,当两个P-MEM对于它们各自的分离获得“0”时,从系统中的缓冲器之一读出小区从从属设备 主机,这使得ATM交换机具有通过相互异步双工的交换机 主动和备份系统切换系统,而不会导致单元被重复或丢失。
    • 10. 发明授权
    • Signaling data receiving and processing unit provided in a broadband
integrated services digital network
    • 在宽带综合业务数字网络中提供的信令数据接收和处理单元
    • US5369649A
    • 1994-11-29
    • US731332
    • 1991-07-17
    • Masami MurayamaSatoshi KakumaShuji Yoshimura
    • Masami MurayamaSatoshi KakumaShuji Yoshimura
    • H04L1/00H04L12/951H04M7/00H04Q11/04G06F11/10
    • H04Q11/0478H04L2012/563
    • An error check of a signaling data divided into divided signaling data transferred asynchronously in a unit of cells is performed in a signaling data receiving and processing unit in a digital exchange. The exchange is connected with terminal equipment arranged in a narrow band ISDN environment in a broadband ISDN system. The error check is performed by calculating an error check code for every byte of the signaling data as it is received, accumulating the result until the cyclic redundancy code, encountered in the last byte of the signaling data, is accumulated and performing matching between the accumulated result and a constant value produced based on the CRC system. The checking is performed while the signaling data is stored in a data memory in the signaling data receiving and processing unit. The data memory provided in the signaling data receiving and processing unit has memory regions capable of storing the signaling data sent from the terminal which is allocated as needed by a central controller of the digital exchange.
    • 在数字交换中的信令数据接收和处理单元中执行分组为以小区为单位异步传送的分离信令数据的信令数据的错误检查。 该交换机与宽带ISDN系统中布置在窄带ISDN环境中的终端设备连接。 通过计算接收到的信令数据的每个字节的错误校验码来进行错误检查,累加结果,直到在信令数据的最后一个字节中遇到的循环冗余码被累积并执行累积的 结果和基于CRC系统产生的恒定值。 当信令数据存储在信令数据接收和处理单元中的数据存储器中时,执行检查。 提供在信令数据接收和处理单元中的数据存储器具有能够存储从数字交换机的中央控制器根据需要分配的从终端发送的信令数据的存储区域。