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    • 11. 发明申请
    • Cache memory and cache memory control apparatus
    • 高速缓冲存储器和高速缓冲存储器控制装置
    • US20100030966A1
    • 2010-02-04
    • US12458053
    • 2009-06-30
    • Taichi HiraoNaotaka OsawaKoichi Hasegawa
    • Taichi HiraoNaotaka OsawaKoichi Hasegawa
    • G06F12/08G06F12/00
    • G06F12/0859
    • Disclosed herein is a cache memory including: a tag storage section including entries each including a tag address and a pending indication portion, at least one of the entries being to be referred to by a first address portion of an access address; a data storage section; a tag control section configured to compare a second address portion of the access address with the tag address included in each of the entries referred to to detect an entry whose tag address matches the second address portion, and, when the pending indication portion included in the detected entry indicates pending, cause an access related to the access address to be suspended; and a data control section configured to select data corresponding to the detected entry from among the data storage section, when the pending indication portion included in the detected entry does not indicate pending.
    • 本文公开了一种高速缓冲存储器,包括:标签存储部分,其包括各自包括标签地址和未决指示部分的条目,所述条目中的至少一个将由访问地址的第一地址部分引用; 数据存储部分; 标签控制部分,被配置为将访问地址的第二地址部分与参考的每个条目中包括的标签地址进行比较,以检测其标签地址与第二地址部分匹配的条目,并且当包括在 检测到的条目指示挂起,导致访问地址相关的访问被暂停; 以及数据控制部分,被配置为当所检测的条目中包括的未决指示部分未指示未决时,从数据存储部分中选择与所检测的条目相对应的数据。
    • 13. 发明授权
    • Optical encoder, method for preparing the optical encoder, and moving speed controlling device and apparatus using the optical encoder
    • 光学编码器,光学编码器的制备方法以及使用光学编码器的移动速度控制装置和装置
    • US07548306B2
    • 2009-06-16
    • US12213743
    • 2008-06-24
    • Koichi Hasegawa
    • Koichi Hasegawa
    • G01P3/36
    • G01D11/245
    • An optical encoder including a sensor module including a light emitting member, a light receiving member opposite to the light emitting member to receive the emitted light, and at least one boss extending in a first direction; a shade member located between the light emitting member and the light receiving member and having a shading pattern; a first support supporting the sensor module and including at least one recessed portion engaged with the boss, and a groove connected with the recessed portion and extending in a second direction, wherein the sensor module is attached to the first support by being moved in the second direction while the boss is guided by the groove, and wherein the recessed portion has a depth greater than the height of the boss, and a portion of the groove adjacent to the recessed portion has a depth less than the height of the boss.
    • 一种光学编码器,包括:传感器模块,包括发光部件;与所述发光部件相对的光接收部件,用于接收发光;以及至少一个凸起,其沿第一方向延伸; 位于所述发光部件和所述受光部件之间并具有遮光图案的遮光部件; 支撑所述传感器模块并且包括与所述凸台接合的至少一个凹部的第一支撑件和与所述凹部连接并沿第二方向延伸的凹槽,其中所述传感器模块通过在所述第二支撑件中移动而附接到所述第一支撑件 方向,同时凸起由凹槽引导,并且其中凹部的深度大于凸台的高度,并且与凹部相邻的凹槽的一部分的深度小于凸台的高度。
    • 17. 发明授权
    • Clock frequency divider circuit
    • 时钟分频电路
    • US07205800B2
    • 2007-04-17
    • US11274256
    • 2005-11-16
    • Koichi Hasegawa
    • Koichi Hasegawa
    • H03K21/00H03K23/00H03K25/00
    • H03K23/52
    • A clock frequency divider circuit including: a storing section for storing an input signal in synchronism with an input clock signal; a supplying section for supplying, as the input signal, one of a first value obtained by adding a value stored by the storing section to a numerator setting value and a second value obtained by subtracting a denominator setting value from the first value; a retaining section for retaining a most significant bit of the value stored by the storing section in synchronism with the input clock signal; and a logical product generating section for generating a logical product of a value retained by the retaining section and the input clock signal, and outputting the logical product as an output clock signal; wherein the supplying section supplies one of the first value and the second value as the input signal on a basis of the most significant bit of the value stored by the storing section.
    • 一种时钟分频器电路,包括:存储部分,用于与输入时钟信号同步地存储输入信号; 提供部分,用于将通过将存储部分存储的值相加得到的第一值作为输入信号提供给分子设置值,以及通过从第一值中减去分母设置值而获得的第二值; 保持部分,用于与输入时钟信号同步地保存由存储部分存储的值的最高有效位; 以及逻辑积生成单元,生成由所述保持单元保存的值与所述输入时钟信号的逻辑积,并输出所述逻辑积作为输出时钟信号; 其中所述供应部分基于由所述存储部分存储的所述值的最高有效位提供所述第一值和所述第二值中的一个作为所述输入信号。
    • 20. 发明授权
    • Light-emitting diode
    • 发光二极管
    • US5665984A
    • 1997-09-09
    • US705095
    • 1996-08-29
    • Koichi HasegawaIsao Kabe
    • Koichi HasegawaIsao Kabe
    • H01L33/30H01L33/00
    • H01L33/30H01L33/0025
    • A light-emitting diode comprises a first layer of Si-doped N-type Ga.sub.1-x Al.sub.x As, a second layer of Si-doped P-type Ga.sub.1-y Al.sub.y As and a third layer of P-type Ga.sub.1-z Al.sub.z As, in that order, in which the first and third layers have a higher Al concentration than the second layer, an Al concentration in the second layer decreases going from a first layer side to a third layer side, an Al concentration in a portion of the second layer in contact with the third layer is higher than an Al concentration value in a portion of the second layer in contact with the first layer minus 0.06, the second layer is formed to a thickness of approximately 8 .mu.m to 50 .mu.m, and light emission is via the first layer.
    • 发光二极管依次包括第一层Si掺杂的N型Ga 1-x Al x As,第二层Si掺杂的P型Ga1-yAlyAs和第三层P型Ga1-zAlzAs, 其中第一和第三层具有比第二层更高的Al浓度,第二层中的Al浓度从第一层侧减小到第三层侧,第二层的与第二层接触的部分中的Al浓度 与第一层接触的第二层的部分中的Al浓度值高于第二层的0.06%,第二层形成厚度约为8μm〜50μm,发光通过第一层 层。