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1. 发明申请

US20100030966A1 Cache memory and cache memory control apparatus 审中-公开
标题翻译：高速缓冲存储器和高速缓冲存储器控制装置
公开(公告)号：US20100030966A1
公开(公告)日：2010-02-04
申请号：US12458053
申请日：2009-06-30
申请人： Taichi Hirao , Naotaka Osawa , Koichi Hasegawa
发明人： Taichi Hirao , Naotaka Osawa , Koichi Hasegawa
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0859
摘要： Disclosed herein is a cache memory including: a tag storage section including entries each including a tag address and a pending indication portion, at least one of the entries being to be referred to by a first address portion of an access address; a data storage section; a tag control section configured to compare a second address portion of the access address with the tag address included in each of the entries referred to to detect an entry whose tag address matches the second address portion, and, when the pending indication portion included in the detected entry indicates pending, cause an access related to the access address to be suspended; and a data control section configured to select data corresponding to the detected entry from among the data storage section, when the pending indication portion included in the detected entry does not indicate pending.
摘要翻译：本文公开了一种高速缓冲存储器，包括：标签存储部分，其包括各自包括标签地址和未决指示部分的条目，所述条目中的至少一个将由访问地址的第一地址部分引用; 数据存储部分; 标签控制部分，被配置为将访问地址的第二地址部分与参考的每个条目中包括的标签地址进行比较，以检测其标签地址与第二地址部分匹配的条目，并且当包括在检测到的条目指示挂起，导致访问地址相关的访问被暂停; 以及数据控制部分，被配置为当所检测的条目中包括的未决指示部分未指示未决时，从数据存储部分中选择与所检测的条目相对应的数据。

2. 发明授权

US08650385B2 Instruction fetch apparatus, processor and program counter addition control method 有权
标题翻译：指令提取装置，处理器和程序计数器附加控制方法
公开(公告)号：US08650385B2
公开(公告)日：2014-02-11
申请号：US13024580
申请日：2011-02-10
申请人： Hitoshi Kai , Hiroaki Sakaguchi , Hiroshi Kobayashi , Katsuhiko Metsugi , Haruhisa Yamamoto , Yousuke Morita , Koichi Hasegawa , Taichi Hirao
发明人： Hitoshi Kai , Hiroaki Sakaguchi , Hiroshi Kobayashi , Katsuhiko Metsugi , Haruhisa Yamamoto , Yousuke Morita , Koichi Hasegawa , Taichi Hirao
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/321 , G06F9/30101 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3804 , G06F9/3842
摘要： An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an increment value on the program counter; an increment value register configured to hold the changed increment value; and an addition control section configured such that if the change designation register designates the change of the increment value on the program counter, then the addition control section increments the program counter based on the changed increment value held in the increment value register, the addition control section further incrementing the program counter by an instruction word length if the change designation register does not designate any change of the increment value on the program counter.
摘要翻译：一种提取指令装置，其特征在于包括：程序计数器，被配置为在其中顺序放置属于多个指令序列的指令的程序中管理目标要执行的指令的地址; 变更指定寄存器，被配置为指定所述程序计数器上的增量值的变化; 增量值寄存器，被配置为保持所述改变的增量值; 以及附加控制部分，其被配置为使得如果所述改变指定寄存器指定所述程序计数器上的所述增量值的改变，则所述相加控制部分基于所述增量值寄存器中保持的改变的增量值来增加所述程序计数器，所述加法控制如果改变指定寄存器没有指定程序计数器上的增量值的任何改变，则进一步将程序计数器递增指令字长度。

3. 发明申请

US20110238952A1 INSTRUCTION FETCH APPARATUS, PROCESSOR AND PROGRAM COUNTER ADDITION CONTROL METHOD 有权
标题翻译：指令设备，处理器和程序计数器附加控制方法
公开(公告)号：US20110238952A1
公开(公告)日：2011-09-29
申请号：US13024580
申请日：2011-02-10
申请人： Hitoshi Kai , Hiroaki Sakaguchi , Hiroshi Kobayashi , Katsuhiko Metsugi , Haruhisa Yamamoto , Yousuke Morita , Koichi Hasegawa , Taichi Hirao
发明人： Hitoshi Kai , Hiroaki Sakaguchi , Hiroshi Kobayashi , Katsuhiko Metsugi , Haruhisa Yamamoto , Yousuke Morita , Koichi Hasegawa , Taichi Hirao
IPC分类号： G06F9/38
CPC分类号： G06F9/321 , G06F9/30101 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3804 , G06F9/3842
摘要： An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an increment value on the program counter; an increment value register configured to hold the changed increment value; and an addition control section configured such that if the change designation register designates the change of the increment value on the program counter, then the addition control section increments the program counter based on the changed increment value held in the increment value register, the addition control section further incrementing the program counter by an instruction word length if the change designation register does not designate any change of the increment value on the program counter.
摘要翻译：一种提取指令装置，其特征在于包括：程序计数器，被配置为在其中顺序放置属于多个指令序列的指令的程序中管理目标要执行的指令的地址; 变更指定寄存器，被配置为指定所述程序计数器上的增量值的变化; 增量值寄存器，被配置为保持所述改变的增量值; 以及附加控制部分，其被配置为使得如果所述改变指定寄存器指定所述程序计数器上的所述增量值的改变，则所述相加控制部分基于所述增量值寄存器中保持的改变的增量值来增加所述程序计数器，所述加法控制如果改变指定寄存器没有指定程序计数器上的增量值的任何改变，则进一步将程序计数器递增指令字长度。

4. 发明授权

US09535841B2 Cache memory and cache memory control unit 有权
标题翻译：缓存内存和缓存内存控制单元
公开(公告)号：US09535841B2
公开(公告)日：2017-01-03
申请号：US13515315
申请日：2010-12-14
申请人： Taichi Hirao , Hiroaki Sakaguchi , Hiroshi Yoshikawa , Masaaki Ishii
发明人： Taichi Hirao , Hiroaki Sakaguchi , Hiroshi Yoshikawa , Masaaki Ishii
IPC分类号： G06F13/00 , G06F12/08
CPC分类号： G06F12/084 , G06F12/0806 , G06F12/0808 , G06F12/12 , G06F12/128 , G06F2212/314 , G06F2212/69
摘要： Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.
摘要翻译：在包括共享高速缓冲存储器的多处理器中有效地执行处理器之间的数据传输。除了标签地址字段221，有效字段222和脏字段223之外，高速缓冲存储器的标签存储部分220中的每个条目保存参考数字段224.参考号字段224被设置在数据写入中，并且其值在每次读取访问之后递减。当参考号字段224的值从“1”改变为“0”时，该条目无效而不执行回写操作。当高速缓冲存储器用于多处理器系统中的处理器之间的通信时，高速缓冲存储器用作共享FIFO，并且使用的数据被自动删除。

5. 发明申请

US20120331234A1 CACHE MEMORY AND CACHE MEMORY CONTROL UNIT 有权
标题翻译：高速缓存存储器和高速缓存存储器控制单元
公开(公告)号：US20120331234A1
公开(公告)日：2012-12-27
申请号：US13515315
申请日：2010-12-14
申请人： Taichi Hirao , Hiroaki Sakaguchi , Hiroshi Yoshikawa , Masaaki Ishii
发明人： Taichi Hirao , Hiroaki Sakaguchi , Hiroshi Yoshikawa , Masaaki Ishii
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0806 , G06F12/0808 , G06F12/12 , G06F12/128 , G06F2212/314 , G06F2212/69
摘要： Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.
摘要翻译：在包括共享高速缓冲存储器的多处理器中有效地执行处理器之间的数据传输。除了标签地址字段221，有效字段222和脏字段223之外，高速缓冲存储器的标签存储部分220中的每个条目保存参考数字段224.参考号字段224被设置在数据写入中，并且其值在每次读取访问之后递减。当参考号字段224的值从1变为0时，该条目无效而不执行回写操作。当高速缓冲存储器用于多处理器系统中的处理器之间的通信时，高速缓冲存储器用作共享FIFO，并且使用的数据被自动删除。

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