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11. 发明申请

US20080091928A1 Branch lookahead prefetch for microprocessors 有权
标题翻译：用于微处理器的分支前瞻预取
公开(公告)号：US20080091928A1
公开(公告)日：2008-04-17
申请号：US11953799
申请日：2007-12-10
申请人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and determining the validity of data utilized by the speculative execution. Dispatch logic determines the validity of the data by marking one or more registers of an instruction dispatch unit to indicate which results of the pending instructions are invalid. The speculative execution of instructions can occur across multiple pipeline stages of the microprocessor, and the validity of the data is tracked during their execution in the multiple pipeline stages while monitoring a dependency of the speculatively executed instructions relative to one another during their execution in the multiple pipeline stages.
摘要翻译：一种处理微处理器中的程序指令的方法，其通过在执行程序指令期间检测到失速状态的发生来减少与错误预测的分支指令相关联的延迟，推测性地执行一个或多个未决指令，其中包括在失速期间包括至少一个分支指令条件，并确定投机执行使用的数据的有效性。调度逻辑通过标记指令调度单元的一个或多个寄存器来指示待处理指令的哪些结果无效来确定数据的有效性。指令的推测执行可以在微处理器的多个流水线阶段发生，并且在多个流水线阶段的执行期间跟踪数据的有效性，同时在多个流水线阶段的执行期间监视推测性执行的指令相对于彼此的依赖性流水线阶段

12. 发明申请

US20060184946A1 Thread priority method, apparatus, and computer program product for ensuring processing fairness in simultaneous multi-threading microprocessors 失效
标题翻译：线程优先方法，装置和计算机程序产品，用于确保同时多线程微处理器的处理公平性
公开(公告)号：US20060184946A1
公开(公告)日：2006-08-17
申请号：US11055850
申请日：2005-02-11
申请人： James Bishop , Hung Le , Dung Nguyen , Balaram Sinharoy , Brian Thompto , Raymond Yeung
发明人： James Bishop , Hung Le , Dung Nguyen , Balaram Sinharoy , Brian Thompto , Raymond Yeung
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4818 , G06F9/485
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.
摘要翻译：在数据处理系统中公开了一种方法，装置和计算机程序产品，用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性。在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

13. 发明申请

US20060149935A1 Load lookahead prefetch for microprocessors 失效
公开(公告)号：US20060149935A1
公开(公告)日：2006-07-06
申请号：US11016236
申请日：2004-12-17
申请人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838 , G06F9/3851
摘要： The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such future load instructions can be prefetched from a distant cache or main memory such that when the load instruction is re-executed (non speculative executed) after the stall condition expires, its data will reside either in the L1 cache, or will be enroute to the processor, resulting in a reduced execution latency. When an extended stall condition is detected, load lookahead prefetch is started allowing speculative execution of instructions that would normally have been stalled. In this speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available via forwarding and are not written to the architected registers. A set of status bits are used to dynamically keep track of the dependencies between instructions in the pipeline and a bit vector tracks invalid architected facilities with respect to the speculative instruction stream. Both sources of information are used to identify load instructions with valid operands for calculating the load address. If the operands are valid, then a load prefetch operation is started to retrieve data from the cache ahead of time such that it can be available for the load instruction when it is non-speculatively executed.

14. 发明申请

US20150052413A1 DECODING OF LDPC CODE 有权
标题翻译： LDPC码的解码
公开(公告)号：US20150052413A1
公开(公告)日：2015-02-19
申请号：US14358609
申请日：2011-05-25
申请人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Dung Nguyen
发明人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Dung Nguyen
IPC分类号： H03M13/11
CPC分类号： H03M13/1105 , H03M13/1108 , H03M13/2957
摘要： It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity.
摘要翻译：提供了一种用于解码由LPDC码编码的比特序列的方法。该方法包括提供一组位状态，包括第一状态和第二状态，以及一组条件以改变包括第一条件5和第二状态的位状态。第一个条件和第二个条件是不同的。该方法包括读取序列的每个比特的值，根据读取的值将每个比特与组的相应状态相关联，确定满足评估条件并改变目标比特的状态作为结果条件得到满足然后，该方法可以根据其状态设置10序列的目标比特的值。这种方法提供了一种解码方案，用于以比典型的比特翻转算法更好的性能来解码由LDPC码编码的比特序列，只有稍微增加的复杂度。

15. 发明授权

US08315254B2 Bandwidth management switching card 有权
标题翻译：带宽管理交换卡
公开(公告)号：US08315254B2
公开(公告)日：2012-11-20
申请号：US12635174
申请日：2009-12-10
申请人： Boris Reynov , Euan Mowat , Venkata Penmetsa , Shreeram Siddhaye , Jack Kohn , Dung Nguyen
发明人： Boris Reynov , Euan Mowat , Venkata Penmetsa , Shreeram Siddhaye , Jack Kohn , Dung Nguyen
IPC分类号： H04L12/28 , H04L12/50 , H04L12/66 , G06F15/173
CPC分类号： H04L49/10 , H04L49/15
摘要： A bandwidth management card includes a switch control unit and multiple ports connected to one or more line cards that are separate from the bandwidth management card. The bandwidth management card further includes at least one switch, and multiple network ports, where each of the multiple network ports is connected to a respective link to at least one external network. A first switch of the at least one switch receives instructions from the switch control unit, switches a first subset of the multiple network ports through to a first port of the multiple ports based on the received instructions, and switches a second subset of the multiple network ports through to a second port of the multiple ports based on the received first instructions.
摘要翻译：带宽管理卡包括开关控制单元和连接到与带宽管理卡分离的一个或多个线路卡的多个端口。带宽管理卡还包括至少一个交换机和多个网络端口，其中多个网络端口中的每一个连接到至少一个外部网络的相应链路。所述至少一个交换机的第一交换机从所述交换机控制单元接收指令，基于所接收的指令将所述多个网络端口的第一子集切换到所述多个端口的第一端口，并且切换所述多个网络的第二子集基于所接收的第一指令，端口到达多个端口的第二端口。

16. 发明授权

US07236269B2 System and method for dithering with reduced memory 有权
标题翻译：减少记忆抖动的系统和方法
公开(公告)号：US07236269B2
公开(公告)日：2007-06-26
申请号：US10288781
申请日：2002-11-05
申请人： Timothy J. Donovan , Dung Nguyen , Meng Long
发明人： Timothy J. Donovan , Dung Nguyen , Meng Long
IPC分类号： H04N1/405
CPC分类号： G09G3/2059
摘要： A dithering system yielding two-dimensional dither functioning is implemented without line memories. For each primary input color, a feedback loop outputs an color input signal plus error that can be preset to different values. The desired result is that vertical artifacts on a display formed from the output signals are relocated to different locations on consecutive display lines. If signal magnitude from the feedback loop output exceeds the magnitude of the video system creating the display, signal magnitude is preset to a value representing error at the start of the display line.
摘要翻译：实现了产生二维抖动功能的抖动系统而没有行存储器。对于每个主要输入颜色，反馈回路输出颜色输入信号加上可以预设为不同值的错误。期望的结果是，由输出信号形成的显示器上的垂直伪像被重定位到连续显示行上的不同位置。如果来自反馈环路输出的信号幅度超过创建显示器的视频系统的幅度，信号幅度被预设为表示在显示行开始处的误差的值。

17. 发明申请

US20070171708A1 Multi-level memory cell sensing 有权
标题翻译：多级存储单元感应
公开(公告)号：US20070171708A1
公开(公告)日：2007-07-26
申请号：US11320529
申请日：2005-12-28
申请人： Kerry Tedrow , Dung Nguyen , Bo Li , Rezaul Haque , Ahsanur Rahman , Saad Monasa , Matthew Goldman
发明人： Kerry Tedrow , Dung Nguyen , Bo Li , Rezaul Haque , Ahsanur Rahman , Saad Monasa , Matthew Goldman
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C7/1048 , G11C16/28 , G11C2211/5634 , G11C2211/5642 , G11C2211/5644 , G11C2211/5645
摘要： A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.
摘要翻译：多级单元存储器件通过在字线上提供阶梯电压波形并将单元电流与基本恒定的参考电流进行比较来执行读取。在应用阶梯电压波形之前，字线可以与另一个电路节点共享电荷。

18. 发明申请

US20060212143A1 Apparatus and methods for instant messaging feature for communication between users in multiple-user information handling system 审中-公开
标题翻译：用于即时通讯功能的装置和方法，用于多用户信息处理系统中用户之间的通信
公开(公告)号：US20060212143A1
公开(公告)日：2006-09-21
申请号：US11069283
申请日：2005-03-01
申请人： Dung Nguyen , Alaa Yousif
发明人： Dung Nguyen , Alaa Yousif
IPC分类号： G05B19/18 , G05B15/02
CPC分类号： G05B19/042 , G05B2219/23237 , G05B2219/24166 , H04L51/04
摘要： An information handling system includes a host computer and a remote access controller. A plurality of remote users communicate with the host computer. The remote access controller communicates an instant message from one of the remote users to one or more of the remote users. The instant message communicates information related to administration, use, access, and/or management of the at least one resource of the host computer.
摘要翻译：信息处理系统包括主计算机和远程访问控制器。多个远程用户与主机通信。远程访问控制器将来自远程用户之一的即时消息传送给一个或多个远程用户。即时消息传达与主计算机的至少一个资源的管理，使用，访问和/或管理有关的信息。

19. 发明申请

US20060179100A1 System and method for performing floating point store folding 失效
标题翻译：执行浮点存储折叠的系统和方法
公开(公告)号：US20060179100A1
公开(公告)日：2006-08-10
申请号：US11054686
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
发明人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
IPC分类号： G06F7/38
CPC分类号： G06F9/3826 , G06F9/30014 , G06F9/3824 , G06F9/3838 , G06F9/3885
摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.
摘要翻译：一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

20. 发明申请

US20060168393A1 Apparatus and method for dependency tracking and register file bypass controls using a scannable register file 审中-公开
标题翻译：使用可扫描寄存器文件的依赖关系跟踪和寄存器文件旁路控制的装置和方法
公开(公告)号：US20060168393A1
公开(公告)日：2006-07-27
申请号：US11044567
申请日：2005-01-27
申请人： Bjorn Christensen , Peter Klim , Dung Nguyen , Raymond Yeung
发明人： Bjorn Christensen , Peter Klim , Dung Nguyen , Raymond Yeung
IPC分类号： G06F12/14
CPC分类号： G06F9/30141 , G06F9/30134 , G06F9/3828 , G06F9/3838 , G06F9/3867
摘要： An apparatus and method for dependency tracking and register file bypass controls using a scannable register file are provided. With the apparatus and method, a scannable register file array is provided and used to track the stage of any instruction in the execution unit. Every entry in the target vector is updated every cycle to stay synchronized with the instructions in the execution unit. To keep the register file array synchronized with the instructions in the execution unit, a right shift of all the data in each entry of the register file array occurs every cycle. The scan port of the register file array cells is used as the shift function.
摘要翻译：提供了使用可扫描寄存器文件的依赖关系跟踪和寄存器文件旁路控制的装置和方法。利用该装置和方法，提供可扫描的寄存器文件阵列并用于跟踪执行单元中任何指令的阶段。每个周期更新目标向量中的每个条目，以与执行单元中的指令保持同步。为了使寄存器文件阵列与执行单元中的指令保持同步，每个周期都会发生寄存器文件阵列的每个条目中所有数据的右移。寄存器文件阵列单元的扫描端口用作移位功能。

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