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1. 发明申请

US20110142065A1 BANDWIDTH MANAGEMENT SWITCHING CARD 有权
标题翻译：带宽管理切换卡
公开(公告)号：US20110142065A1
公开(公告)日：2011-06-16
申请号：US12635174
申请日：2009-12-10
申请人： Boris REYNOV , Euan MOWAT , Venkata PENMETSA , Shreeram SIDDHAYE , Jack KOHN , Dung Nguyen
发明人： Boris REYNOV , Euan MOWAT , Venkata PENMETSA , Shreeram SIDDHAYE , Jack KOHN , Dung Nguyen
IPC分类号： H04L12/56
CPC分类号： H04L49/10 , H04L49/15
摘要： A bandwidth management card includes a switch control unit and multiple ports connected to one or more line cards that are separate from the bandwidth management card. The bandwidth management card further includes at least one switch, and multiple network ports, where each of the multiple network ports is connected to a respective link to at least one external network. A first switch of the at least one switch receives instructions from the switch control unit, switches a first subset of the multiple network ports through to a first port of the multiple ports based on the received instructions, and switches a second subset of the multiple network ports through to a second port of the multiple ports based on the received first instructions.
摘要翻译：带宽管理卡包括开关控制单元和连接到与带宽管理卡分离的一个或多个线路卡的多个端口。带宽管理卡还包括至少一个交换机和多个网络端口，其中多个网络端口中的每一个连接到至少一个外部网络的相应链路。所述至少一个交换机的第一交换机从所述交换机控制单元接收指令，基于所接收的指令将所述多个网络端口的第一子集切换到所述多个端口的第一端口，并且切换所述多个网络的第二子集基于所接收的第一指令，端口到达多个端口的第二端口。

2. 发明授权

US08315254B2 Bandwidth management switching card 有权
标题翻译：带宽管理交换卡
公开(公告)号：US08315254B2
公开(公告)日：2012-11-20
申请号：US12635174
申请日：2009-12-10
申请人： Boris Reynov , Euan Mowat , Venkata Penmetsa , Shreeram Siddhaye , Jack Kohn , Dung Nguyen
发明人： Boris Reynov , Euan Mowat , Venkata Penmetsa , Shreeram Siddhaye , Jack Kohn , Dung Nguyen
IPC分类号： H04L12/28 , H04L12/50 , H04L12/66 , G06F15/173
CPC分类号： H04L49/10 , H04L49/15
摘要： A bandwidth management card includes a switch control unit and multiple ports connected to one or more line cards that are separate from the bandwidth management card. The bandwidth management card further includes at least one switch, and multiple network ports, where each of the multiple network ports is connected to a respective link to at least one external network. A first switch of the at least one switch receives instructions from the switch control unit, switches a first subset of the multiple network ports through to a first port of the multiple ports based on the received instructions, and switches a second subset of the multiple network ports through to a second port of the multiple ports based on the received first instructions.
摘要翻译：带宽管理卡包括开关控制单元和连接到与带宽管理卡分离的一个或多个线路卡的多个端口。带宽管理卡还包括至少一个交换机和多个网络端口，其中多个网络端口中的每一个连接到至少一个外部网络的相应链路。所述至少一个交换机的第一交换机从所述交换机控制单元接收指令，基于所接收的指令将所述多个网络端口的第一子集切换到所述多个端口的第一端口，并且切换所述多个网络的第二子集基于所接收的第一指令，端口到达多个端口的第二端口。

3. 发明申请

US20150052413A1 DECODING OF LDPC CODE 有权
标题翻译： LDPC码的解码
公开(公告)号：US20150052413A1
公开(公告)日：2015-02-19
申请号：US14358609
申请日：2011-05-25
申请人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Dung Nguyen
发明人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Dung Nguyen
IPC分类号： H03M13/11
CPC分类号： H03M13/1105 , H03M13/1108 , H03M13/2957
摘要： It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity.
摘要翻译：提供了一种用于解码由LPDC码编码的比特序列的方法。该方法包括提供一组位状态，包括第一状态和第二状态，以及一组条件以改变包括第一条件5和第二状态的位状态。第一个条件和第二个条件是不同的。该方法包括读取序列的每个比特的值，根据读取的值将每个比特与组的相应状态相关联，确定满足评估条件并改变目标比特的状态作为结果条件得到满足然后，该方法可以根据其状态设置10序列的目标比特的值。这种方法提供了一种解码方案，用于以比典型的比特翻转算法更好的性能来解码由LDPC码编码的比特序列，只有稍微增加的复杂度。

4. 发明授权

US07236269B2 System and method for dithering with reduced memory 有权
标题翻译：减少记忆抖动的系统和方法
公开(公告)号：US07236269B2
公开(公告)日：2007-06-26
申请号：US10288781
申请日：2002-11-05
申请人： Timothy J. Donovan , Dung Nguyen , Meng Long
发明人： Timothy J. Donovan , Dung Nguyen , Meng Long
IPC分类号： H04N1/405
CPC分类号： G09G3/2059
摘要： A dithering system yielding two-dimensional dither functioning is implemented without line memories. For each primary input color, a feedback loop outputs an color input signal plus error that can be preset to different values. The desired result is that vertical artifacts on a display formed from the output signals are relocated to different locations on consecutive display lines. If signal magnitude from the feedback loop output exceeds the magnitude of the video system creating the display, signal magnitude is preset to a value representing error at the start of the display line.
摘要翻译：实现了产生二维抖动功能的抖动系统而没有行存储器。对于每个主要输入颜色，反馈回路输出颜色输入信号加上可以预设为不同值的错误。期望的结果是，由输出信号形成的显示器上的垂直伪像被重定位到连续显示行上的不同位置。如果来自反馈环路输出的信号幅度超过创建显示器的视频系统的幅度，信号幅度被预设为表示在显示行开始处的误差的值。

5. 发明授权

US07575161B2 Systems and methods for pre-scanning merchandise in customer's shopping cart while customer is waiting in checkout line 有权
标题翻译：客户在结帐线上等待客户购物车中的商品预扫描的系统和方法
公开(公告)号：US07575161B2
公开(公告)日：2009-08-18
申请号：US10641421
申请日：2003-08-15
申请人： Dung Nguyen , Aime V. Rodriguez
发明人： Dung Nguyen , Aime V. Rodriguez
IPC分类号： G06K15/00
CPC分类号： G06K7/10861 , A47F9/047 , B62B5/0096 , G07G1/0054
摘要： Systems and methods for pre-scanning retail merchandise. A mobile scanning station includes a frame, and a pair of arms mounted to the frame, positioned to hold an open bag for receiving pre-scanned items. A platform is mounted to the frame, positioned under the pair of arms for providing a supporting surface for items contained in an open bag held by the pair of arms. The frame further includes an EAS deactivator support for holding an EAS deactivator for deactivating EAS tags on pre-scanned items before they are placed in the open bag.
摘要翻译：零售商品预扫描系统和方法。移动扫描站包括框架和安装到框架的一对臂，定位成保持用于接收预扫描物品的打开的袋子。平台被安装到框架上，位于一对臂下方，用于为包含在由一对臂保持的开放袋中的物品提供支撑表面。该框架还包括EAS去激活器支持，用于保持EAS去激活器，用于在预先扫描的物品放置在开放袋中之前停用EAS标签。

6. 发明申请

US20080077776A1 Load Lookahead Prefetch for Microprocessors 有权
标题翻译：加载用于微处理器的前瞻预取
公开(公告)号：US20080077776A1
公开(公告)日：2008-03-27
申请号：US11950495
申请日：2007-12-05
申请人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838 , G06F9/3851
摘要： The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such future load instructions can be prefetched from a distant cache or main memory such that when the load instruction is re-executed (non speculative executed) after the stall condition expires, its data will reside either in the L1 cache, or will be enroute to the processor, resulting in a reduced execution latency. When an extended stall condition is detected, load lookahead prefetch is started allowing speculative execution of instructions that would normally have been stalled. In this speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available via forwarding and are not written to the architected registers. A set of status bits are used to dynamically keep track of the dependencies between instructions in the pipeline and a bit vector tracks invalid architected facilities with respect to the speculative instruction stream. Both sources of information are used to identify load instructions with valid operands for calculating the load address. If the operands are valid, then a load prefetch operation is started to retrieve data from the cache ahead of time such that it can be available for the load instruction when it is non-speculatively executed.
摘要翻译：本发明允许微处理器在失速状态期间识别并推测性地执行未来的加载指令。这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。可以从远程高速缓存或主存储器预取这样的未来加载指令的数据，使得当停止条件到期之后，当加载指令被重新执行（不推测执行）时，其数据将驻留在L1高速缓存中，或者将进入处理器，导致执行时间缩短。当检测到扩展失速条件时，启动加载前瞻预取，允许推测执行通常已经停止的指令。在这种推测模式中，由于缺少L1高速缓存的源负载，设备在推测执行模式下不可用的设备，或由于不能通过转发而不能使用并且未写入到架构化寄存器的推测性指令结果，指令操作数可能无效。一组状态位用于动态地跟踪流水线中的指令之间的依赖关系，并且位向量相对于推测性指令流跟踪无效的架构设施。两个信息来源用于识别加载指令，其中包含用于计算加载地址的有效操作数。如果操作数有效，则启动加载预取操作以提前从高速缓存中检索数据，使得当非推测性地执行加载指令时，可以对加载指令可用。

7. 发明申请

US20060179282A1 Method using hazard vector to enhance issue throughput of dependent instructions in a microprocessor 失效
标题翻译：使用危险向量的方法来增强微处理器中依赖指令的问题吞吐量
公开(公告)号：US20060179282A1
公开(公告)日：2006-08-10
申请号：US11054289
申请日：2005-02-09
申请人： Hung Le , Dung Nguyen , Raymond Yeung
发明人： Hung Le , Dung Nguyen , Raymond Yeung
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3834 , G06F9/3838 , G06F9/3867
摘要： A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing a first instruction, such as an FMA instruction, to move through the sequence of execution stages, the first instruction being directed to a specified one of the registers. The method further includes issuing a second instruction to move through the execution stages, the second instruction being issued after the first instruction has issued, but before the first instruction reaches the final write back stage. The second instruction is likewise directed to the specified register, and comprises either a store instruction or a load instruction, selectively. R and W bits corresponding to the specified register are used to ensure that a store instruction does not read data from, and that a load instruction does not write data to the specified register, respectively, before the first instruction is moved to the final write back stage.
摘要翻译：提供了一种用于具有多个寄存器的处理器的方法和相关装置，其中顺序地发出指令以从初始阶段到最终回写阶段移动经过一系列执行阶段。作为一种方法，实施例包括发出诸如FMA指令的第一指令以移动经过执行级序列的步骤，第一指令被引导到指定的一个寄存器。该方法还包括发出第二指令以移动通过执行阶段，第二指令在第一指令发出之后但在第一指令到达最终回写阶段之前发出。第二条指令同样针对指定的寄存器，并且选择性地包括存储指令或加载指令。使用与指定寄存器相对应的R和W位来确保存储指令不会从第一指令移动到最终回写之前分别读取数据，并且加载指令不会将数据写入指定的寄存器阶段。

8. 发明申请

US20060149934A1 Using a modified value GPR to enhance lookahead prefetch 失效
标题翻译：使用修改值GPR来增强前瞻预取
公开(公告)号：US20060149934A1
公开(公告)日：2006-07-06
申请号：US11016206
申请日：2004-12-17
申请人： Richard Eickemever , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemever , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838
摘要： The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future instructions can initiate a prefetch of data or instructions from a distant cache or main memory, or otherwise make forward progress through the instruction stream. In this manner, when the instructions are re-executed (non speculatively executed) after the stall condition expires, they will execute with a reduced execution latency; e.g. by accessing data prefetched into the L1 cache, or enroute to the processor, or by executing the target instructions following a speculatively resolved mispredicted branch. In speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available. Dependency and dirty (i.e. invalid result) bits are tracked and used to determine which speculative instructions are valid for execution. A modified value register storage and bit vector are used to improve the availability of speculative results that would otherwise be discarded once they leave the execution pipeline because they cannot be written to the architected registers. The modified general purpose registers are used to store speculative results when the corresponding instruction reaches writeback and the modified bit vector tracks the results that have been stored there. Younger speculative instructions that do not bypass directly from older instructions will then use this modified data when the corresponding bit in the modified bit vector indicates the data has been modified. Otherwise, data from the architected registers will be used.
摘要翻译：本发明允许微处理器在失速状态期间识别和推测地执行未来的指令。这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。这样的未来指令的执行可以启动来自远程高速缓存或主存储器的数据或指令的预取，或以其他方式通过指令流进行进展。以这种方式，当在停止条件到期之后重新执行（不推测地执行）指令时，它们将以降低的执行延迟执行; 例如通过访问预取到L1高速缓存中的数据，或者进入处理器，或通过在推测性地解决的误预测分支之后执行目标指令。在推测模式中，由于缺少L1缓存的源加载，在推测执行模式下不可用的设备，或由于不可用的推测指令结果，指令操作数可能无效。跟踪依赖关系和脏（即无效结果）位，并用于确定哪些推测指令对执行有效。改进的值寄存器存储和位向量被用于提高推测结果的可用性，否则，由于不能将其写入到架构化的寄存器，否则将抛弃执行流水线。修改后的通用寄存器用于在对应指令到达回写时存储推测结果，修改后的位向量跟踪存储在其中的结果。当修改的位向量中的相应位指示数据已被修改时，不直接从旧指令旁路的较小的推测指令将使用该修改的数据。否则，将使用来自架构化寄存器的数据。

9. 发明申请

US20060149933A1 Branch lookahead prefetch for microprocessors 失效
标题翻译：用于微处理器的分支前瞻预取
公开(公告)号：US20060149933A1
公开(公告)日：2006-07-06
申请号：US11016200
申请日：2004-12-17
申请人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and determining the validity of data utilized by the speculative execution. In particular, the method can detect a load instruction miss which results in the stall condition. Dispatch logic determines the validity of the data by marking one or more registers of an instruction dispatch unit to indicate which results of the pending instructions are invalid. The speculative execution of instructions can occur across multiple pipeline stages of the microprocessor, and the validity of the data is tracked during their execution in the multiple pipeline stages while monitoring a dependency of the speculatively executed instructions relative to one another during their execution in the multiple pipeline stages. A branch prediction unit predicts a path of the branch instruction prior to detection of the stall condition, and fetches speculative instructions from the predicted path into an instruction queue. If the speculative execution of the branch instruction indicates it was mispredicted, the speculative instructions are flushed from the pipeline and instruction queue, and the branch prediction information is updated based on results of the speculative execution of the branch instruction. The speculative execution of the instructions occurs without altering any architected facilities of the microprocessor.
摘要翻译：一种处理微处理器中的程序指令的方法，其通过在执行程序指令期间检测到失速状态的发生来减少与错误预测的分支指令相关联的延迟，推测性地执行一个或多个未决指令，其中包括在失速期间包括至少一个分支指令条件，并确定投机执行使用的数据的有效性。特别地，该方法可以检测到导致失速状态的加载指令未命中。调度逻辑通过标记指令调度单元的一个或多个寄存器来指示待处理指令的哪些结果无效来确定数据的有效性。指令的推测执行可以在微处理器的多个流水线阶段发生，并且在多个流水线阶段的执行期间跟踪数据的有效性，同时在多个流水线阶段的执行期间监视推测性执行的指令相对于彼此的依赖性流水线阶段分支预测单元在检测到停顿条件之前预测分支指令的路径，并且从预测路径获取推测指令到指令队列中。如果分支指令的推测执行指示它被错误预测，则从流水线和指令队列刷新推测指令，并且基于分支指令的推测执行的结果更新分支预测信息。指令的推测执行不会改变微处理器的任何架构设计。

10. 发明申请

US20050029052A1 Methods and apparatus for improved register checkout 审中-公开
标题翻译：改进注册结算的方法和装置
公开(公告)号：US20050029052A1
公开(公告)日：2005-02-10
申请号：US10937569
申请日：2004-09-09
申请人： Dung Nguyen
发明人： Dung Nguyen
IPC分类号： A47F9/04 , A63F9/02
CPC分类号： A47F9/046 , A47F9/045
摘要： Systems and techniques for more efficient checkout are described. A triangular carousel having a relatively small footprint is employed proximate a bar code scanner and point of sale (POS) terminal so that a checker can efficiently load scanned items into bags, and a customer on the other side of the checkout counter and proximate the bar code scanner can also efficiently load filled bags into his or her shopping cart.
摘要翻译：描述了用于更有效的结帐的系统和技术。在条形码扫描器和销售点（POS）终端附近使用具有相对较小占地面积的三角形转盘，使得检验器可以有效地将扫描的物品加载到袋中，并且在结帐柜台的另一侧和接近条形码的客户代码扫描器也可以将填充的袋子有效地加载到他或她的购物车中。

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