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11. 发明授权

US6087275A Reduction of n-channel parasitic transistor leakage by using low power/low pressure phosphosilicate glass 失效
标题翻译：通过使用低功率/低压磷硅玻璃减少n沟道寄生晶体管泄漏
公开(公告)号：US6087275A
公开(公告)日：2000-07-11
申请号：US843150
申请日：1997-04-26
申请人： Minh Van Ngo , Sunil D. Mehta , Nicholas R. MacCrae
发明人： Minh Van Ngo , Sunil D. Mehta , Nicholas R. MacCrae
IPC分类号： H01L21/316 , H01L21/762 , H01L21/768 , H01L21/8234 , H01L21/31
CPC分类号： H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/31625 , H01L21/76202 , H01L21/76895 , H01L21/823481
摘要： A method of manufacturing a semiconductor device with increasing threshold voltage for parasitic transistor by forming a low power-low pressure phosphosilicate glass layer on the active regions and the field oxide regions.
摘要翻译：一种通过在有源区域和场氧化物区域上形成低功率 - 低压磷硅玻璃层来制造用于寄生晶体管的阈值电压增加的半导体器件的方法。

12. 发明授权

US6075293A Semiconductor device having a multi-layer metal interconnect structure 有权
标题翻译：具有多层金属互连结构的半导体器件
公开(公告)号：US6075293A
公开(公告)日：2000-06-13
申请号：US263412
申请日：1999-03-05
申请人： Xiao-Yu Li , Sunil D. Mehta , Van H. Pham , Amit P. Marathe
发明人： Xiao-Yu Li , Sunil D. Mehta , Van H. Pham , Amit P. Marathe
IPC分类号： H01L23/532 , H01L23/48
CPC分类号： H01L23/53223 , H01L2924/0002
摘要： A multi-level metal interconnect structure in a semiconductor device includes a plurality of overlying metal layers separated by ILD layers and electrically connected by filled vias in the ILD layers. Each metal layer includes a relatively thick antireflective layer for improved electromigration resistance. Each metal layer also includes a metal lining layer and a metal interconnect layer overlying the metal lining layer. Enhanced electromigration resistance is obtained by forming the antireflective layer to a thickness of no less than the thickness of the metal lining layer. In a preferred embodiment of the invention, the antireflective layer has a thickness of about 1000 angstroms.
摘要翻译：半导体器件中的多级金属互连结构包括由ILD层分离并由ILD层中的填充通孔电连接的多个上覆金属层。每个金属层包括相对较厚的抗反射层，用于改善电迁移阻力。每个金属层还包括覆盖金属衬里层的金属衬里层和金属互连层。通过将抗反射层形成为不小于金属衬里层的厚度的厚度来获得增强的电迁移电阻。在本发明的优选实施例中，抗反射层的厚度为约1000埃。

13. 发明授权

US6064595A Floating gate memory apparatus and method for selected programming thereof 有权
标题翻译：浮栅存储装置及其选择编程方法
公开(公告)号：US6064595A
公开(公告)日：2000-05-16
申请号：US220201
申请日：1998-12-23
申请人： Stewart G. Logie , Sunil D. Mehta , Steven J. Fong
发明人： Stewart G. Logie , Sunil D. Mehta , Steven J. Fong
IPC分类号： H01L21/8247 , G11C16/04 , G11C16/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/0441 , G11C16/10 , H01L29/7886
摘要： A method of creating a reverse breakdown condition in an array of memory cells arranged in columns and rows in the array, and an array structure are provided. The method comprises the steps of applying a first voltage on a first column connection coupling a first column of said cells, and a second voltage on a second column connection coupling a second column of said cells; and applying a third voltage on a first row connection coupling a first row of said cells, and applying said second voltage on a second row connection coupling a second row of said cells. In this aspect, the difference between the first voltage and the third voltage creates said reverse breakdown condition in at least one cell occupying said first column and first row. In a further aspect, each cell includes a floating gate and the method of the invention includes the step of programming one of said cells by coupling a control voltage to each floating gate. The structure includes a substrate having formed therein at least an Nth or Mth row-wise oriented well, each well isolated from adjacent ones of said wells. Also provided are at least an Nth and Mth word bit line formed by an Nth and Mth impurity regions in said substrate and at least an Nth and Mth array control gate lines. A plurality of memory cells, each cell formed in at least said Nth or Mth row-wise well, is further provided. Each cell comprises a drain, a floating gate, a drain connection one of said Nth or Mth word bit line (WBL), and a substrate well connection to one of said Nth or Mth wells, and a control gate connection to one of said Nth or Mth array control gate lines(ACG).
摘要翻译：提供了在阵列中以行和列排列的存储单元阵列中产生反向故障条件的方法，以及阵列结构。该方法包括以下步骤：在耦合所述单元的第一列的第一列连接上施加第一电压，以及在耦合所述单元的第二列的第二列连接上施加第二电压; 以及在耦合所述单元的第一行的第一行连接上施加第三电压，以及将耦合所述单元的第二行的第二行连接上施加所述第二电压。在这方面，第一电压和第三电压之间的差异在占据所述第一列和第一行的至少一个单元中产生所述反向击穿条件。在另一方面，每个单元包括浮动栅极，并且本发明的方法包括通过将控制电压耦合到每个浮动栅极来编程所述单元之一的步骤。该结构包括在其中形成有至少第N或第M行行取向阱的衬底，每个阱与相邻的所述阱分离。还提供了由所述衬底中的第N和第M杂质区形成的至少第N和第M字位线以及至少第N和第M阵列控制栅极线。还提供多个存储单元，每个单元形成在至少所述第N或第M行列井中。每个单元包括所述第N或第M字位线（WBL）之一的漏极，浮置栅极，漏极连接以及与所述第N或第M阱之一的衬底阱连接，以及到所述第N个或第M阵列控制栅极线（ACG）。

14. 发明授权

US6060766A Protection of hydrogen sensitive regions in semiconductor devices from the positive charge associated with plasma deposited barriers or layers 失效
标题翻译：从与等离子体沉积的屏障或层相关的正电荷保护半导体器件中的氢敏感区域
公开(公告)号：US6060766A
公开(公告)日：2000-05-09
申请号：US918244
申请日：1997-08-25
申请人： Sunil D. Mehta , William G. En
发明人： Sunil D. Mehta , William G. En
IPC分类号： H01L21/336 , H01L23/26 , H01L23/485 , H01L29/06
CPC分类号： H01L29/66825 , H01L23/26 , H01L23/485 , H01L2924/0002 , H01L2924/13091
摘要： A semiconductor device with first and second types of devices formed in a semiconductor substrate with a barrier layer formed over the surface of the semiconductor device including over the first and second types of devices with the barrier layer removed from over the first type of device. The first type of device is a positive charge sensitive device such as a nonvolatile memory device. The semiconductor device has a hydrogen getter layer formed under the barrier layer.
摘要翻译：一种具有第一和第二类型器件的半导体器件，其形成在具有阻挡层的半导体衬底中，所述阻挡层形成在所述半导体器件的表面上，包括在所述第一和第二类型器件之上，所述阻挡层从所述第一类型器件上方移除。第一种类型的器件是正电荷敏感器件，例如非易失性存储器件。半导体器件具有在阻挡层下形成的吸氢剂层。

15. 再颁专利

USRE40311E1 Zero-power programmable memory cell 有权
标题翻译：零功率可编程存储单元
公开(公告)号：USRE40311E1
公开(公告)日：2008-05-13
申请号：US11206282
申请日：2005-08-17
申请人： Sunil D. Mehta , Fabiano Fontana
发明人： Sunil D. Mehta , Fabiano Fontana
IPC分类号： G11C16/04
CPC分类号： G11C16/045 , G11C16/0441
摘要： A zero-power electrically erasable and programmable memory cell is implemented in CMOS (complementary metal oxide semiconductor) technology. A P-channel sense transistor has a source coupled to a first voltage generator, and an N-channel sense transistor has a source coupled to a second voltage generator. The drains of the P-channel and N-channel sense transistors are coupled together to form an output of the memory cell, and the gates of the P-channel and N-channel sense transistor are coupled together to form a floating gate of the memory cell. In an example embodiment of the present invention, each of the first and second voltage generators are variable voltage generators that apply a positive voltage at the respective source of each of the P-channel and N-channel sense transistors during the erase operation and/or that apply a ground or negative voltage at the respective source of each of the P-channel and N-channel sense transistors during the program operation. In another embodiment of the present invention, a magnitude of the respective threshold voltage of each of the P-channel and N-channel sense transistors is higher than a magnitude of a threshold voltage of standard process P-channel and N-channel transistors. With such a higher threshold voltage, the P-channel and N-channel sense transistors do not erroneously turn on to dissipate power during the read operation, to ensure that the memory cell is a zero-power memory cell.
摘要翻译：在CMOS（互补金属氧化物半导体）技术中实现零功率电可擦除和可编程存储器单元。 P沟道感测晶体管具有耦合到第一电压发生器的源极，并且N沟道感测晶体管具有耦合到第二电压发生器的源极。 P沟道和N沟道感测晶体管的漏极耦合在一起以形成存储单元的输出，并且P沟道和N沟道读出晶体管的栅极耦合在一起以形成存储器的浮置栅极细胞。在本发明的示例性实施例中，第一和第二电压发生器中的每一个是在擦除操作期间在每个P沟道和N沟道读出晶体管的各个源处施加正电压的可变电压发生器和/或其在编程操作期间在每个P沟道和N沟道感测晶体管的相应源处施加接地或负电压。在本发明的另一个实施例中，每个P沟道和N沟道检测晶体管的相应阈值电压的大小都高于标准工艺P沟道和N沟道晶体管的阈值电压的幅度。利用这种较高的阈值电压，P信道和N沟道检测晶体管在读取操作期间不会错误地导通以耗散功率，以确保存储器单元是零功率存储单元。

16. 发明授权

US06846714B1 Voltage limited EEPROM device and process for fabricating the device 失效
标题翻译：电压限制EEPROM器件和制造器件的工艺
公开(公告)号：US06846714B1
公开(公告)日：2005-01-25
申请号：US10263507
申请日：2002-10-03
申请人： Sunil D. Mehta , Kerry Ilgenstein
发明人： Sunil D. Mehta , Kerry Ilgenstein
IPC分类号： G11C16/30 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/105 , G11C16/30 , H01L27/115 , H01L27/11521 , H01L27/11558 , Y10S438/981
摘要： An EEPROM device having voltage limiting charge pumping circuitry includes charge pumping circuitry that limits the voltage supplied to the high voltage transistors to levels below the breakdown field of the tunnel oxide layer. The EEPROM device includes a substrate having a programming region, a tunnel region, a sensing region, and a low voltage region. A first oxide layer having a first thickness overlies the tunnel region and the sensing region. A second oxide layer having a second thickness overlies the low voltage region. The first oxide thickness is greater than the second oxide thickness. A charge pumping circuit is coupled to the programming region and to the tunnel region. The charge pumping circuit impresses a voltage level across the first oxide layer that is below the field breakdown voltage of first oxide layer. A process for fabricating the device is also provided.
摘要翻译：具有电压限制电荷泵浦电路的EEPROM器件包括电荷泵浦电路，其将提供给高压晶体管的电压限制在低于隧道氧化物层的击穿场的水平。 EEPROM器件包括具有编程区域，隧道区域，感测区域和低电压区域的衬底。具有第一厚度的第一氧化物层覆盖隧道区域和感测区域。具有第二厚度的第二氧化物层覆盖在低电压区域上。第一氧化物厚度大于第二氧化物厚度。电荷泵浦电路耦合到编程区域和隧道区域。电荷泵浦电路使第一氧化物层的电压电平低于第一氧化物层的场击穿电压。还提供了一种用于制造该装置的工艺。

17. 发明授权

US06600188B1 EEPROM with a neutralized doping at tunnel window edge 失效
标题翻译：在隧道窗边缘具有中和掺杂的EEPROM
公开(公告)号：US06600188B1
公开(公告)日：2003-07-29
申请号：US10083728
申请日：2002-02-26
申请人： Chun Jiang , Sunil D. Mehta
发明人： Chun Jiang , Sunil D. Mehta
IPC分类号： H01L27108
CPC分类号： H01L29/0847 , H01L21/28273 , H01L29/66825 , H01L29/7883
摘要： An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. P-type lightly-doped drain regions are located at the polysilicon edges of the tunnel window. During the programming operation, the P-type lightly-doped drain regions are in contacting with the polysilicon edges. As a result, there is reduced or suppressed the tunneling current to the program junction region so as to improve the efficiency of programming.
摘要翻译：提供了一种用于制造用于EEPROM存储单元的隧道氧化物窗口的改进方法，以便产生更好的编程耐久性。 P型轻掺杂漏极区位于隧道窗的多晶硅边缘处。在编程操作期间，P型轻掺杂漏极区域与多晶硅边缘接触。结果，减少或抑制了到程序结区域的隧穿电流，从而提高编程效率。

18. 发明授权

US06455375B1 Eeprom tunnel window for program injection via P+ contacted inversion 失效
标题翻译： Eeprom隧道窗口通过P +接触反转进行程序注入
公开(公告)号：US06455375B1
公开(公告)日：2002-09-24
申请号：US09870541
申请日：2001-06-01
申请人： Chun Jiang , Robert Tu , Sunil D. Mehta
发明人： Chun Jiang , Robert Tu , Sunil D. Mehta
IPC分类号： H01L218247
CPC分类号： H01L21/28273
摘要： An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. A P+ implant is provided at the tunnel window edge. During the programming operation, the P+ contacted inversion layer is used instead of the program junction. As a result, there is eliminated the voltage drop in the program junction region so as to improve the efficiency of programming.
摘要翻译：提供了一种用于制造用于EEPROM存储单元的隧道氧化物窗口的改进方法，以便产生更好的编程耐久性。在隧道窗边缘提供P +植入物。在编程操作期间，使用P +接触反转层代替程序结。结果，消除了程序结区域中的电压降，从而提高编程效率。

19. 发明授权

US06309942B1 STI punch-through defects and stress reduction by high temperature oxide reflow process 有权
标题翻译： STI穿透缺陷和通过高温氧化物回流工艺的应力降低
公开(公告)号：US06309942B1
公开(公告)日：2001-10-30
申请号：US09245161
申请日：1999-02-04
申请人： Ting Y. Tsui , Robert H. Tu , Xiao-Yu Li , Sunil D. Mehta
发明人： Ting Y. Tsui , Robert H. Tu , Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150° C. to about 1200° C.
摘要翻译：公开了一种制造具有减小的浅沟槽隔离缺陷和应力的半导体器件的方法。所公开的方法开始于提供包括封盖层的硅衬底。然后通过覆盖层蚀刻多个隔离沟槽并进入硅衬底，以在硅衬底中形成多个隔离区域。然后用氧化物层填充隔离沟槽。然后使用本领域已知的技术将氧化物层和覆盖层进行抛光。在抛光之后，半导体器件在约1150℃至约1200℃的温度范围内退火

20. 发明授权

US06297128B1 Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress 失效
标题翻译：用于制造具有低机械应力的电介质材料的浅沟槽的制造方法
公开(公告)号：US06297128B1
公开(公告)日：2001-10-02
申请号：US09240560
申请日：1999-01-29
申请人： Hyeon-Seag Kim , Sunil D. Mehta
发明人： Hyeon-Seag Kim , Sunil D. Mehta
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： This invention provides methods for reducing the mechanical stresses within dielectric layers filling the gaps in shallow trench isolation (STI) regions on semiconductor wafers. The methods include the sequential deposition of alternating layers of dielectric materials having tensile stress and compressive stress, respectively. The invention also provides methods for adjusting the residual stress in a dielectric film by controlling the relative thicknesses of the alternating layers of dielectric material to provide bilayers having minimal overall stress. Additionally, the invention provides semiconductor devices having the reduced stress dielectric materials within the shallow isolation trenches of the semiconductor wafer. The reduction in stress within and between trenches decreases defects in the shallow isolation materials and thereby decreases source-drain and trench—trench short circuiting. The improved electrical and mechanical properties of the shallow trench filling materials makes practical the manufacture of more reliable, smaller semiconductor devices.
摘要翻译：本发明提供了减少填充半导体晶片上的浅沟槽隔离（STI）区域中的间隙的电介质层内的机械应力的方法。这些方法包括分别具有拉伸应力和压缩应力的交替层的介电材料的顺序沉积。本发明还提供了通过控制介电材料的交替层的相对厚度以提供具有最小总应力的双层来调节电介质膜中的残余应力的方法。此外，本发明提供了在半导体晶片的浅隔离沟槽内具有减小的应力介电材料的半导体器件。沟槽内和沟槽之间的应力减小降低了浅隔离材料的缺陷，从而减少了源极 - 漏极和沟槽沟槽短路。浅沟槽填充材料的改进的电气和机械性能使得制造更可靠，更小的半导体器件成为可能。

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