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11. 发明授权

US07345507B1 Multi-product die configurable as two or more programmable integrated circuits of different logic capacities 有权
标题翻译：多产品管芯可配置为具有不同逻辑容量的两个或多个可编程集成电路
公开(公告)号：US07345507B1
公开(公告)日：2008-03-18
申请号：US11333991
申请日：2006-01-17
申请人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
发明人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.
摘要翻译：多产品集成电路管芯包括至少两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。选择码存储电路存储产品选择码。产品选择代码的第一个值选择第一模具的第一和第二部分都可操作的选项。产品选择代码的第二个值选择仅第一个模具的第一部分可操作的选项。选择代码存储电路可以包括非易失性存储器或熔丝结构，或者可以将产品选择代码配置为封装绑定选项。产品选择代码还可以为模具的操作部分启用边界扫描，并且从边界扫描链中省略故意使其不可操作的模具的任何部分。

12. 发明授权

US06204691B1 FPGA with a plurality of input reference voltage levels grouped into sets 有权
标题翻译： FPGA具有多个输入参考电压电平分组成组
公开(公告)号：US06204691B1
公开(公告)日：2001-03-20
申请号：US09569745
申请日：2000-05-11
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： H03K19094
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

13. 发明授权

US06448809B2 FPGA with a plurality of input reference voltage levels 有权
标题翻译： FPGA具有多个输入参考电压电平
公开(公告)号：US06448809B2
公开(公告)日：2002-09-10
申请号：US09924356
申请日：2001-08-07
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F738
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

14. 发明授权

US6049227A FPGA with a plurality of I/O voltage levels 有权
标题翻译：具有多个I / O电压电平的FPGA
公开(公告)号：US6049227A
公开(公告)日：2000-04-11
申请号：US187666
申请日：1998-11-05
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F7/38 , H03K19/003 , H03K19/094 , H03K19/177 , H03K19/0175 , H03K19/082
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

15. 发明授权

US07499513B1 Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit 有权
标题翻译：用于在集成电路中提供频率合成和相位对准的方法和装置
公开(公告)号：US07499513B1
公开(公告)日：2009-03-03
申请号：US11049329
申请日：2005-02-02
申请人： David E. Tetzlaff , F. Erich Goetting , Steven P. Young , Marwan M. Hassoun , Moises E. Robinson
发明人： David E. Tetzlaff , F. Erich Goetting , Steven P. Young , Marwan M. Hassoun , Moises E. Robinson
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： G06F1/10 , H03L7/07 , H03L7/0891 , H03L7/095 , H03L7/183
摘要： According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.
摘要翻译：根据特定示例性实施例，集成电路包括一个或多个串行数据发送器。每个这样的数据发射器被布置成在集成电路的相应数据输出端口上发送数据，其中用于至少一个数据发射器的相应数据输出端口专用于发送用于对相应目标电路计时的周期性数据。在涉及反馈的其他具体实施例中，在可编程逻辑器件（PLD）的功能块中实现了锁相环（PLL）信号控制和/或延迟锁定环（DLL）信号控制。 PLD响应于源时钟并且包括可配置逻辑阵列，其包括可配置逻辑块和可配置路由块，并且用于至少一个数据发射器的相应数据输出端口提供相应的目标时钟。

16. 发明授权

US07491576B1 Yield-enhancing methods of providing a family of scaled integrated circuits 有权
标题翻译：提供一系列缩放集成电路的产量增强方法
公开(公告)号：US07491576B1
公开(公告)日：2009-02-17
申请号：US11333990
申请日：2006-01-17
申请人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
发明人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
IPC分类号： H01L21/66 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L22/22 , H01L23/544 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.
摘要翻译：制造集成电路管芯（例如，可编程逻辑器件（PLD）管芯），其具有被配置为至少两个不同尺寸的家庭部件的能力。在封装之前测试IC芯片。如果IC芯片的第一部分是完全功能的，但是第二部分包括局部缺陷，则IC芯片被封装成产品选择代码，所述产品选择代码构成IC裸片仅作为芯片的第一部分进行操作。死亡的第二部分故意使其不能运作。因此，IC芯片仍然可以作为全功能封装IC出售。

17. 发明授权

US07402443B1 Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes 有权
标题翻译：使用产品选择代码为集成电路系列提供类似模具的方法部分禁用
公开(公告)号：US07402443B1
公开(公告)日：2008-07-22
申请号：US11333819
申请日：2006-01-17
申请人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
发明人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
IPC分类号： G01R31/26
CPC分类号： H01L27/11807 , H01L27/0207
摘要： A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.
摘要翻译：提供集成电路（IC）系列的方法包括：将第一产品选择代码（PSC）应用于第一IC芯片，将第二PSC应用于第二IC芯片，以及提供第三封装IC芯片。第一IC芯片包括第一和第二部分，它们都基于第一PSC而可操作。第二IC芯片是第一裸片的副本，但是第二部分由第二PSC不可操作。第三IC管芯基本上类似于第一管芯的第一部分。第二和第三包可以是相同的，并且包装的模具可以在系统中互换。当管芯是可编程逻辑器件（PLD）管芯时，第二和第三管芯使用与第一IC管芯的配置位流相同的配置位流。

18. 发明授权

US06294930B1 FPGA with a plurality of input reference voltage levels 有权
标题翻译： FPGA具有多个输入参考电压电平
公开(公告)号：US06294930B1
公开(公告)日：2001-09-25
申请号：US09479392
申请日：2000-01-06
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F738
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

19. 发明授权

US5877632A FPGA with a plurality of I/O voltage levels 失效
标题翻译：具有多个I / O电压电平的FPGA
公开(公告)号：US5877632A
公开(公告)日：1999-03-02
申请号：US837023
申请日：1997-04-11
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F7/38 , H03K19/003 , H03K19/094 , H03K19/177 , H03K19/0948
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。

20. 发明授权

US08001511B1 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies 有权
标题翻译：在多产品可编程IC芯片的可选边界实现和建模互连线路的方法
公开(公告)号：US08001511B1
公开(公告)日：2011-08-16
申请号：US12245858
申请日：2008-10-06
申请人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
发明人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： H03K19/177 , G06F17/5054 , G06F17/5068
摘要： A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.
摘要翻译：使用相同的软件模型对两个IC芯片建模的方法，尽管两个芯片包括物理差异。第一可编程逻辑器件（PLD）管芯包括第一和第二部分，并被编码以使第一部分可操作，第二部分不可操作。在两部分之间的边界处，穿过边界的互连线包括第一部分中的第一部分和第二部分中的第二部分。第二PLD管芯包括第一PLD管芯的第一部分，同时省略第二部分。延伸到第二管芯边缘的互连线成对连接在一起。两个芯片的软件模型包括一个省略对耦合的终端模型，增加了对省略连接进行补偿的RC负载，以及（对于双向互连线），标记每对中的一条互连线，因为无法使用路由软件。

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