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11. 发明申请

US20060110892A1 Semiconductor process for forming stress absorbent shallow trench isolation structures 有权
标题翻译：用于形成应力吸收性浅沟槽隔离结构的半导体工艺
公开(公告)号：US20060110892A1
公开(公告)日：2006-05-25
申请号：US10996319
申请日：2004-11-22
申请人： Marius Orlowski , Mark Foisy , Olubunmi Adetutu
发明人： Marius Orlowski , Mark Foisy , Olubunmi Adetutu
IPC分类号： H01L21/76
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/76229 , H01L21/823807 , H01L21/823878
摘要： A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.
摘要翻译：半导体制造工艺包括在半导体衬底上图案化硬掩模以暴露隔离区域并在隔离区域中形成沟槽。在沟槽中沉积可流动电介质以部分地填充沟槽，并且覆盖覆盖第一氧化物的覆盖电介质以填充沟槽。衬底可以是包括掩埋氧化物（BOX）层的绝缘体上硅（SOI）衬底，并且沟槽可以部分地延伸到BOX层中。可流动电介质可以是自旋沉积的可流动氧化物或CVD BPSG氧化物。可流动介电隔离结构提供了缓冲器，其防止在隔离结构的一侧上引起的应力在结构的另一侧上产生应力。因此，例如，通过在PMOS区域中的硅上形成硅锗产生的压缩应力在NMOS区域中不产生压应力。

12. 发明申请

US20050277294A1 Method for treating a semiconductor surface to form a metal-containing layer 有权
标题翻译：用于处理半导体表面以形成含金属层的方法
公开(公告)号：US20050277294A1
公开(公告)日：2005-12-15
申请号：US10865268
申请日：2004-06-10
申请人： James Schaeffer , Darrell Roan , Dina Triyoso , Olubunmi Adetutu
发明人： James Schaeffer , Darrell Roan , Dina Triyoso , Olubunmi Adetutu
IPC分类号： C23C16/02 , H01L21/314 , H01L21/316 , H01L21/44
CPC分类号： H01L21/02181 , C23C16/0272 , H01L21/3141 , H01L21/31645
摘要： A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely covering the exposed surface of the semiconductor substrate. The one or more metals enhance nucleation for subsequent material growth. A metal-containing layer is formed on the exposed surface of the semiconductor substrate that has been treated. The treatment of the exposed surface of the semiconductor substrate assists the metal-containing layer to coalesce. In one embodiment, treatment of the exposed surface to enhance nucleation may be performed by spin-coating, atomic layer deposition (ALD), physical layer deposition (PVD), electroplating, or electroless plating. The one or more metals used to treat the exposed surface may include any rare earth or transition metal, such as, for example, hafnium, lanthanum, etc.
摘要翻译：一种用于处理半导体表面以形成含金属层的方法包括提供具有暴露表面的半导体衬底。半导体衬底的暴露表面通过形成覆盖半导体衬底但不完全覆盖半导体衬底的暴露表面的一种或多种金属来处理。一种或多种金属增强成核以用于随后的材料生长。在已经处理的半导体衬底的暴露表面上形成含金属层。半导体衬底的暴露表面的处理有助于含金属层的聚结。在一个实施方案中，可以通过旋涂，原子层沉积（ALD），物理层沉积（PVD），电镀或无电镀来进行暴露表面的处理以增强成核。用于处理暴露表面的一种或多种金属可以包括任何稀土或过渡金属，例如铪，镧等。

13. 发明授权

US06376349B1 Process for forming a semiconductor device and a conductive structure 有权
标题翻译：用于形成半导体器件和导电结构的工艺
公开(公告)号：US06376349B1
公开(公告)日：2002-04-23
申请号：US09487472
申请日：2000-01-19
申请人： Philip J. Tobin , Olubunmi Adetutu , Bikas Maiti
发明人： Philip J. Tobin , Olubunmi Adetutu , Bikas Maiti
IPC分类号： H01L213205
CPC分类号： H01L29/4958 , H01L21/28079
摘要： Semiconductor devices and conductive structures can be formed having a metallic layer. In one embodiment, a semiconductor device includes an amorphous metallic layer (22) and a crystalline metallic layer (42). The amorphous metallic layer (22) helps to reduce the likelihood of penetration of contaminants through the amorphous metallic layer (22). A more conductive crystalline metallic layer (42) can be formed on the amorphous metallic layer (22) to help keep resistivity relatively low. When forming a conductive structure, a metal-containing gas and a scavenger gas flow simultaneously during at least one point in time. The conductive structure may be part of a gate electrode.
摘要翻译：可以形成具有金属层的半导体器件和导电结构。在一个实施例中，半导体器件包括非晶金属层（22）和结晶金属层（42）。无定形金属层（22）有助于降低污染物穿过非晶金属层（22）的可能性。可以在非晶金属层（22）上形成更导电的晶体金属层（42），以帮助保持电阻率相对较低。当形成导电结构时，含金属的气体和清除气体在至少一个时间点内同时流动。导电结构可以是栅电极的一部分。

14. 发明授权

US5888588A Process for forming a semiconductor device 失效
标题翻译：用于形成半导体器件的工艺
公开(公告)号：US5888588A
公开(公告)日：1999-03-30
申请号：US828638
申请日：1997-03-31
申请人： Rajan Nagabushnam , Olubunmi Adetutu , Yeong-Jyh Tom Lii
发明人： Rajan Nagabushnam , Olubunmi Adetutu , Yeong-Jyh Tom Lii
IPC分类号： C23C16/34 , H01L21/28 , H01L29/49 , C23C16/00 , H01L21/285
CPC分类号： C23C16/34 , H01L21/28061 , H01L29/4941
摘要： A semiconductor device (10) includes a gate electrode (61) having a silicon/tungsten nitride/tungsten silicon nitride/tungsten silicide composition. The tungsten nitride film (21) and tungsten suicide film (23) are formed using chemical vapor deposition (CVD). The tungsten nitride film is formed using a tungsten halide and N.sub.2 R.sup.1 R.sup.2, where each of R.sup.1 and R.sup.2 is hydrogen, an alkyl group, an alkenyl group, or an alkynyl group. The tungsten nitride film (21) is an etch stop when patterning the tungsten silicide film (23). The CVD tungsten nitride film (21) helps to improve gate dielectric integrity and reduces interface traps when compared to a sputtered tungsten nitride film (21). Also, N.sub.2 R.sup.1 R.sup.2 can be used to remove halogens that are adsorbed onto walls of a reaction chamber than is cleaned between depositions of substrates.
摘要翻译：半导体器件（10）包括具有硅/氮化钨/氮化钨/硅化钨组合物的栅电极（61）。使用化学气相沉积（CVD）形成氮化钨膜（21）和硅化钨膜（23）。氮化钨膜使用卤化钨和N 2 R 1 R 2形成，其中R 1和R 2各自为氢，烷基，烯基或炔基。当图案化硅化钨膜（23）时，氮化钨膜（21）是蚀刻停止层。与溅射的氮化钨膜（21）相比，CVD氮化钨膜（21）有助于提高栅极电介质完整性并减少界面陷阱。此外，N2R1R2可用于除去吸附到反应室壁上的卤素，而不是在底物沉积之间清洗的卤素。

15. 发明申请

US20080048270A1 ELECTRONIC DEVICE COMPRISING A GATE ELECTRODE INCLUDING A METAL-CONTAINING LAYER HAVING ONE OR MORE IMPURITIES 有权
标题翻译：包含门电极的电子设备，包括具有一个或更多污染物的含金属的层
公开(公告)号：US20080048270A1
公开(公告)日：2008-02-28
申请号：US11928314
申请日：2007-10-30
申请人： Olubunmi Adetutu , David Gilmer , Philip Tobin
发明人： Olubunmi Adetutu , David Gilmer , Philip Tobin
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823842
摘要： One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.
摘要翻译：可以在含金属的栅电极的含金属层内并入一种或多种杂质以改变晶体管的含金属栅电极的功函数可影响晶体管的阈值电压。在一个实施例中，杂质可用于p沟道晶体管，以允许含金属的栅电极的功函数更接近硅的价带。在另一实施例中，杂质可用于n沟道晶体管，以允许含金属的栅电极的功函数更接近于硅的导带。在一个具体的实施方案中，将含硼物质注入到在p沟道晶体管内的含金属栅电极内的含金属层中，使得含金属栅电极具有更接近价带的功函数与没有含硼物质的含金属栅电极相比。

16. 发明申请

US20070134891A1 SOI active layer with different surface orientation 有权
标题翻译：具有不同表面取向的SOI活性层
公开(公告)号：US20070134891A1
公开(公告)日：2007-06-14
申请号：US11302770
申请日：2005-12-14
申请人： Olubunmi Adetutu , Robert Jones , Ted White
发明人： Olubunmi Adetutu , Robert Jones , Ted White
IPC分类号： H01L21/00
CPC分类号： H01L21/76254 , H01L21/02002
摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.
摘要翻译：具有SOI配置的晶片和对不同沟道型晶体管具有不同表面取向的有源区。在一个示例中，在施主晶片上形成具有第一表面取向的半导体结构。具有第二表面取向的半导体结构形成在第二晶片上。受体开口形成在第二晶片上。具有第一表面取向的半导体结构位于接收器开口中并被转移到第二晶片。所得到的晶片具有用于第一沟道型晶体管的具有第一表面取向的半导体区域和具有用于第二沟道型晶体管的第二表面取向的半导体区域。

17. 发明申请

US20060270239A1 Reverse ALD 有权
标题翻译：反向ALD
公开(公告)号：US20060270239A1
公开(公告)日：2006-11-30
申请号：US11139765
申请日：2005-05-27
申请人： Dina Triyoso , Olubunmi Adetutu
发明人： Dina Triyoso , Olubunmi Adetutu
IPC分类号： C23F1/00 , H01L21/461 , H01L21/302 , B44C1/22
CPC分类号： H01L21/0228 , H01L21/02142 , H01L21/02175 , H01L21/265 , H01L21/31111 , H01L21/31116 , H01L21/31122 , H01L21/3141 , H01L21/31645 , H01L21/823462 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor process and apparatus includes forming first and second gate electrodes (151, 161) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). Either or both of the high-k gate dielectric layers (121, 122) may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g., 14). As deposited, the initial layer (14) has an exposed surface (18) and an initial predetermined crystalline structure. An exposed thin surface layer (20) of the initial layer (14) is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.
摘要翻译：半导体工艺和装置包括通过在第一高k栅极电介质（121）上形成第一栅电极（151）并且形成第二栅极电极（161）至少形成第一栅极电极（151,161）与第一栅极电介质（121）不同的第二高k栅极电介质（122）。可以通过沉积和选择性蚀刻高k电介质材料的初始层（例如14）来形成高k栅极电介质层（121,122）之一或两者。沉积时，初始层（14）具有暴露表面（18）和初始预定晶体结构。通过改变暴露的薄表面层中的初始晶体结构，准备初始层（14）的暴露的薄表面层（20）用于蚀刻。暴露的薄表面层中的改性晶体结构可以通过施加选择性蚀刻如HF或HCl来去除。

18. 发明申请

US20060063336A1 Method of forming a semiconductor device having a dielectric layer with high dielectric constant 有权
标题翻译：形成具有高介电常数的介电层的半导体器件的方法
公开(公告)号：US20060063336A1
公开(公告)日：2006-03-23
申请号：US10946938
申请日：2004-09-22
申请人： Dina Triyoso , Olubunmi Adetutu , Randy Cotton
发明人： Dina Triyoso , Olubunmi Adetutu , Randy Cotton
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/3213 , H01L29/513 , H01L29/517 , Y10S438/977 , Y10S438/981
摘要： A method for forming a semiconductor device (10) creates a dielectric layer (18) with high dielectric constant. An interfacial layer (14) is formed over a semiconductor substrate (12). A dielectric layer (16) is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions (24, 26) within the semiconductor substrate.
摘要翻译：一种用于形成半导体器件（10）的方法产生具有高介电常数的介电层（18）。在半导体衬底（12）之上形成界面层（14）。介电层（16）形成在界面层上，其中介电层具有高介电常数（K）。例如通过蚀刻或化学机械抛光，介电层被薄化，其中变薄的介电层的厚度小于稀释之前的电介质层的厚度。在一种形式中，该方法用于形成在半导体衬底内的薄化电介质层和源/漏扩散（24,26）上形成栅电极层的晶体管。

19. 发明授权

US06268289B1 Method for protecting the edge exclusion of a semiconductor wafer from copper plating through use of an edge exclusion masking layer 失效
标题翻译：用于通过使用边缘排除掩蔽层来保护半导体晶片的边缘排除免受镀铜的方法
公开(公告)号：US06268289B1
公开(公告)日：2001-07-31
申请号：US09080809
申请日：1998-05-18
申请人： Rina Chowdhury , Ajay Jain , Olubunmi Adetutu
发明人： Rina Chowdhury , Ajay Jain , Olubunmi Adetutu
IPC分类号： H01L2144
CPC分类号： H01L21/76874 , H01L21/2885 , H01L21/76843 , H01L21/76856 , H01L21/76861 , H01L21/76865 , H01L21/76873 , H01L21/76879 , H01L2221/1089
摘要： A method for forming a copper interconnect begins by depositing a barrier layer (48) within an in-laid region (18). An edge exclusion protection layer (50) is formed over the barrier layer (48), and this layer (50) is processed so that it only lies within the edge exclusion region (20) of the wafer. The layer (50) is removed from active area portions of the wafer so that contact resistance of copper interconnects is not affected. Wet surface processing is used to form a catalyst (64b) on the wafer surface to enable electroless copper plating within active areas of the wafer to form a copper seed layer (52). The layer (52) is not formed in an edge exclusion region (20). Electroplating is then used to thicken the copper material to form a copper layer (54) over the layer (52) wherein the in-laid copper interconnect is completed.
摘要翻译：用于形成铜互连的方法通过在屏蔽区域（18）内沉积阻挡层（48）开始。边缘排除保护层（50）形成在阻挡层（48）上方，并且该层（50）被处理，使得其仅位于晶片的边缘排除区域（20）内。从晶片的有效区域部分去除层（50），使得铜互连的接触电阻不受影响。使用湿表面处理在晶片表面上形成催化剂（64b），以在晶片的有效区域内实现化学镀铜以形成铜籽晶层（52）。层（52）不形成在边缘排除区域（20）中。然后使用电镀来增厚铜材料，以在其上完成嵌入式铜互连的层（52）上形成铜层（54）。

20. 发明授权

US5882243A Method for polishing a semiconductor wafer using dynamic control 失效
标题翻译：使用动态控制来研磨半导体晶片的方法
公开(公告)号：US5882243A
公开(公告)日：1999-03-16
申请号：US839996
申请日：1997-04-24
申请人： Sanjit Das , Subramoney Iyer , Olubunmi Adetutu , Rajeev Bajaj
发明人： Sanjit Das , Subramoney Iyer , Olubunmi Adetutu , Rajeev Bajaj
IPC分类号： B24B37/005 , B24B49/04 , B24B51/00
CPC分类号： B24B37/005 , B24B49/04
摘要： A polishing system (10) is used to polish a semiconductor wafer (16) in accordance with the present invention. Polishing system (10) includes a wafer carrier (14) which includes a modulation unit (20). Modulation unit (20) includes a plurality of capacitors made up of a flexible lower plate (22) and a plurality of smaller upper plate segments (24). A controller (40) monitors the capacitance between each smaller upper plate segment (24) and lower plate (22), and compares the measured capacitance against a predefined set capacitance. To the extent the measured capacitance and predefined capacitance are different, controller (40) adjusts the voltage being applied to the respective upper plate segment (24) so that the measured capacitance and predefined capacitance are aligned. Thus, the present invention is able to achieve dynamic and localized control of the shape of the wafer as it is being polished.
摘要翻译：根据本发明，抛光系统（10）用于抛光半导体晶片（16）。抛光系统（10）包括包括调制单元（20）的晶片载体（14）。调制单元（20）包括由柔性下板（22）和多个较小的上板段（24）组成的多个电容器。控制器（40）监测每个较小的上板段（24）和下板（22）之间的电容，并将测量的电容与预定的设定电容进行比较。在测量电容和预定电容不同的程度上，控制器（40）调节施加到相应的上板段（24）的电压，使得所测量的电容和预定电容对齐。因此，本发明能够在抛光时实现晶片的形状的动态和局部控制。

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