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11. 发明授权

US06466273B1 Analog FIFO memory device 失效
标题翻译：模拟FIFO存储器件
公开(公告)号：US06466273B1
公开(公告)日：2002-10-15
申请号：US09076848
申请日：1998-05-13
申请人： Shiro Dosho , Naoshi Yanagisawa
发明人： Shiro Dosho , Naoshi Yanagisawa
IPC分类号： H04N52136
CPC分类号： G06J1/00
摘要： An analog FIFO memory device allowing for the suppression of the adverse effects produced by fixed pattern noise, generated inside an analog FIFO memory, on signal components. First and second analog multipliers are respectively provided on the input and output sides of the analog FIFO memory. In synchronism with the inputs/outputs of signals to/from the analog FIFO memory, a non-inverting operation and an inverting operation are alternately and repeatedly performed on the input signals and the output signals. Then, although the signal input/output characteristics of the analog FIFO memory are not changed, the fixed pattern noise generated inside the analog FIFO memory is modulated by the second analog multiplier. As a result, the spectrum of the fixed pattern noise, which originally has a lower frequency, is shifted to have a higher frequency. That is to say, since a signal band can be separated from the fixed pattern noise in terms of frequency, the fixed pattern noise can be eliminated by a low pass filter. Consequently, even when the analog FIFO memory device of the present invention is applied for delaying TV signals, the resulting TV image quality is not deteriorated.
摘要翻译：模拟FIFO存储器件允许抑制由模拟FIFO存储器内部产生的固定模式噪声对信号分量产生的不利影响。第一和第二模拟乘法器分别设置在模拟FIFO存储器的输入和输出侧。与来自/来自模拟FIFO存储器的信号的输入/输出同步，对输入信号和输出信号交替重复执行非反相操作和反相操作。然后，虽然模拟FIFO存储器的信号输入/输出特性没有改变，但在模拟FIFO存储器内产生的固定模式噪声被第二模拟乘法器调制。结果，原来具有较低频率的固定图案噪声的频谱被移位以具有较高的频率。也就是说，由于信号频带可以根据频率与固定模式噪声分离，因此可以通过低通滤波器消除固定模式噪声。因此，即使当本发明的模拟FIFO存储器件用于延迟TV信号时，所得到的TV图像质量也不会恶化。

12. 发明授权

US06407642B2 Frequency detector and phase-locked loop circuit including the detector 失效
标题翻译：频率检测器和包括检测器的锁相环电路
公开(公告)号：US06407642B2
公开(公告)日：2002-06-18
申请号：US09752525
申请日：2001-01-03
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama
IPC分类号： H03L7085
CPC分类号： H03D13/004 , H03L7/087 , H03L7/0891 , H03L7/18
摘要： A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width.
摘要翻译：包括两个锁存器和一个“与非”门的三态相位检测器具有两个附加锁存器。为了检测第一和第二输入时钟信号R和V之间的相位差，相位检测器响应于输入R或V信号的上升沿在三个状态之间交替。两个附加锁存器中的每一个和相位检测器中的相关锁存器一起构成一个移位寄存器。当相位检测器回到其中性状态时，与非门产生复位信号，从而复位这四个锁存器的全部。还提供了两个隔离的脉冲发生器。每个脉冲发生器使得从相关联的一个附加锁存器输出的频差脉冲信号的脉冲宽度恒定，然后输出具有恒定宽度的脉冲信号。

13. 发明授权

US06215162B1 Composite MOS transistor device 有权
公开(公告)号：US06215162B1
公开(公告)日：2001-04-10
申请号：US09287310
申请日：1999-04-07
申请人： Masayuki Ozasa , Tatsuo Okamoto , Hidehiko Kurimoto , Shiro Dosho , Kazuhiko Nagaoka
发明人： Masayuki Ozasa , Tatsuo Okamoto , Hidehiko Kurimoto , Shiro Dosho , Kazuhiko Nagaoka
IPC分类号： H01L2976
摘要： A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated. Accordingly, in forming a differential amplifier or a current mirror circuit using this MOS transistor pair, high current gain can be obtained while maintaining an adequate balance in output current.

14. 发明申请

US20050049809A1 Analog circuit automatic calibration system 有权
标题翻译：模拟电路自动校准系统
公开(公告)号：US20050049809A1
公开(公告)日：2005-03-03
申请号：US10915345
申请日：2004-08-11
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
IPC分类号： G01R31/316 , G01R35/00 , G06F19/00
CPC分类号： G01R35/005 , G01R31/316
摘要： An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.
摘要翻译：一种模拟电路自动校准系统，用于校准作为具有随着输入设定值变化的特性的模拟电路的目标电路。该系统包括：设定值存储部分，用于存储值并将该值输出到对象电路作为设定值; 用于检测所述目标电路的特性的特性检测部分; 用于确定所述设定值使得所述对象电路的特性被优化的第一特征变化部分; 第二特征变化部，使用与第一特征变化部中使用的算法不同的算法来更新设定值，使得保持对象电路的特性; 以及选择器，用于选择第一和第二特征部分的输出之一，以使所选择的一个存储在设定值存储部分中。

15. 发明申请

US20090278614A1 PHASE SYNCHRONIZING CIRCUIT 有权
标题翻译：相位同步电路
公开(公告)号：US20090278614A1
公开(公告)日：2009-11-12
申请号：US12096664
申请日：2006-10-25
申请人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
发明人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
IPC分类号： H03L7/08
CPC分类号： H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L7/183 , H03L2207/06
摘要： A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).
摘要翻译：常数确定单元（90）确定各种常数，即从电荷泵电路（30）输出的充电电流的大小，环路滤波器（40）的时间常数和压控振荡器（50）的增益），以使锁相环电路的输入频率和阻尼因子的锁相环电路的固有频率的比例常数成为预定值，并根据确定的常数输出各种控制信号。电荷泵电路（30），环路滤波器（40）和压控振荡器（50）根据从常数输出的控制信号分别修正充电电流的大小，时间常数和增益确定单元（90）。

16. 发明授权

US06528982B1 Jitter detector, phase difference detector and jitter detecting method 失效
标题翻译：抖动检测器，相位差检测器和抖动检测方法
公开(公告)号：US06528982B1
公开(公告)日：2003-03-04
申请号：US09697721
申请日：2000-10-27
申请人： Naoshi Yanagisawa , Shiro Dosho , Kazuhiko Nishikawa , Seiji Watanabe , Takahiro Bokui
发明人： Naoshi Yanagisawa , Shiro Dosho , Kazuhiko Nishikawa , Seiji Watanabe , Takahiro Bokui
IPC分类号： G01R2500
CPC分类号： G01R25/00
摘要： A jitter detector obtains a phase difference between input signals as a digital value to make jitter between the signals easily detectable. The jitter detector includes comparison pulse generator, periodic signal generator, counter and arithmetic unit. The comparison pulse generator outputs one phase difference comparison pulse after another. Each phase difference comparison pulse has a width representing the phase difference between first and second input signals. The periodic signal generator outputs a periodic signal every time a value obtained by accumulating the widths of the phase difference comparison pulses exceeds a predetermined value. Receiving the periodic signal and a clock signal with a period shorter than that of the periodic signal, the counter counts the number of pulses of the clock signal during one period of the periodic signal and outputs a resultant count. And the arithmetic unit detects and outputs a variation in the count as jitter between the first and second input signals.
摘要翻译：抖动检测器获得输入信号之间的相位差作为数字值，使信号之间的抖动容易检测。抖动检测器包括比较脉冲发生器，周期信号发生器，计数器和算术单元。比较脉冲发生器输出一个相差差值比较脉冲。每个相位差比较脉冲具有表示第一和第二输入信号之间的相位差的宽度。每当通过累加相位差比较脉冲的宽度获得的值超过预定值时，周期性信号发生器输出周期信号。接收到周期信号和周期信号的周期信号的时钟信号，计数器在周期信号的一个周期内对时钟信号的脉冲数进行计数，并输出结果计数。并且算术单元检测并输出计数的变化，作为第一和第二输入信号之间的抖动。

17. 发明申请

US20120161990A1 INTEGRATOR AND OVERSAMPLING A/D CONVERTER HAVING THE SAME 有权
标题翻译：集成器和OVERSAMPING A / D转换器
公开(公告)号：US20120161990A1
公开(公告)日：2012-06-28
申请号：US13410964
申请日：2012-03-02
申请人： Shiro Dosho
发明人： Shiro Dosho
IPC分类号： H03M1/12 , G06G7/18
CPC分类号： G06G7/186 , H03H11/12 , H03M3/39 , H03M3/454
摘要： A high order integrator is configured using an operational amplifier, a first filter connected between an input terminal of the integrator and an inverted input terminal of the operational amplifier, and a second filter connected between the inverted input terminal and output terminal of the operational amplifier. The first filter includes n serially-connected first resistance elements, n-1 first capacitance elements each connected between each interconnecting node of the first resistance elements and the ground, and n-1 second resistance elements each connected between each interconnecting node of the first resistance elements and the ground. The second filter includes n serially-connected second capacitance elements, n-1 third resistance elements each connected between each interconnecting node of the second capacitance elements and the ground, and n-1 third capacitance elements each connected between each interconnecting node of the second capacitance elements and the ground.
摘要翻译：高阶积分器使用运算放大器配置，第一滤波器连接在积分器的输入端和运算放大器的反相输入端之间，第二滤波器连接在运算放大器的反相输入端和输出端之间。第一滤波器包括n个串联连接的第一电阻元件，每个连接在第一电阻元件的每个互连节点和地之间的n-1个第一电容元件，以及分别连接在第一电阻的每个互连节点之间的n-1个第二电阻元件元素和地面。第二滤波器包括n个串联连接的第二电容元件，n-1个第三电阻元件，每个连接在第二电容元件的每个互连节点和地之间; n-1个第三电容元件，每个连接在第二电容的每个互连节点之间元素和地面。

18. 发明申请

US20110050476A1 INTEGRATOR, RESONATOR, AND OVERSAMPLING A/D CONVERTER 有权
标题翻译：集成器，谐振器和超滤A / D转换器
公开(公告)号：US20110050476A1
公开(公告)日：2011-03-03
申请号：US12888126
申请日：2010-09-22
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
IPC分类号： H03M1/12 , G06G7/18
CPC分类号： H03M3/454 , H03M3/404 , H03M3/43
摘要： An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n−1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n−1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.
摘要翻译：积分器包括运算放大器，连接到运算放大器的反相输入端的第一滤波器和连接在运算放大器的反相输入端和输出端之间的第二滤波器。第一滤波器包括串联连接的n个电阻元件和（n-1）个电容元件，每个电容元件的一端连接到电阻元件的互连节点，另一端连接到地。第二滤波器包括串联连接的n个电容元件和（n-1）个电阻元件，每个电阻元件的一端连接到电容元件的互连节点，另一端连接到地。

19. 发明授权

US07855670B2 A-to-D converter 有权
公开(公告)号：US07855670B2
公开(公告)日：2010-12-21
申请号：US12749277
申请日：2010-03-29
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
IPC分类号： H03M1/66
CPC分类号： H03M1/46 , H03M1/1215 , H03M1/14 , H03M1/667 , H03M1/682
摘要： A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.

20. 发明授权

US07808295B2 Multiphase level shift system 有权
标题翻译：多相电平转换系统
公开(公告)号：US07808295B2
公开(公告)日：2010-10-05
申请号：US12296021
申请日：2007-06-15
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03L5/00 , H03F3/66
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

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