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1. 发明授权

US5822236A Analog FIFO memory and switching device having a reset operation 失效
标题翻译：具有复位操作的模拟FIFO存储器和开关器件
公开(公告)号：US5822236A
公开(公告)日：1998-10-13
申请号：US863209
申请日：1997-05-27
申请人： Shiro Dosho , Hidehiko Kurimoto , Naoshi Yanagisawa
发明人： Shiro Dosho , Hidehiko Kurimoto , Naoshi Yanagisawa
IPC分类号： G11C27/00 , G11C27/04 , H03H19/00 , H04N9/78
CPC分类号： G11C27/04 , G11C27/00 , H03H19/004 , H04N9/78
摘要： The invention provides an analog FIFO memory from which a written analog signal can be accurately read by eliminating errors in the analog signal between the write operation and the read operation. Prior to the read operation for reading the analog signal from a memory cell through a memory bus, a reset operation for setting the memory bus at a predetermined potential is conducted so as to remove a charge stored in a parasitic capacitance of the memory bus. The input terminal of a read circuit is set at a predetermined potential, with a write circuit disconnected from the memory bus by using an input circuit and with the read circuit connected with the memory bus by using an output circuit. In this manner, the memory bus is set at the predetermined potential, and the charge stored in the parasitic capacitance is discharged. At this point, a switch in each memory cell is in an off-state, and hence, a charge corresponding to the analog signal can be retained in the memory cell.
摘要翻译：本发明提供了一种模拟FIFO存储器，通过消除写入操作和读取操作之间的模拟信号中的错误，可以准确地读取写入的模拟信号。在从存储器单元通过存储器总线读取模拟信号的读取操作之前，进行用于将存储器总线设置在预定电位的复位操作，以便消除存储在存储器总线的寄生电容中的电荷。读取电路的输入端子通过使用输入电路和与存储器总线连接的读取电路通过使用输出电路将写入电路从存储器总线断开而被设置在预定电位。以这种方式，将存储器总线设置在预定电位，并且存储在寄生电容中的电荷被放电。此时，每个存储单元中的开关处于截止状态，因此可以将与模拟信号相对应的电荷保留在存储单元中。

2. 发明授权

US07492216B2 Filtering apparatus for correcting variation of CR-product 失效
标题翻译：用于校正CR产品变化的过滤装置
公开(公告)号：US07492216B2
公开(公告)日：2009-02-17
申请号：US11783059
申请日：2007-04-05
申请人： Hidehiko Kurimoto , Yasuo Oba
发明人： Hidehiko Kurimoto , Yasuo Oba
IPC分类号： H03K5/00
CPC分类号： H03H11/1291 , H03H2210/021 , H03H2210/043
摘要： A filtering apparatus includes a main filter, a variation detection circuit, and a variation correction circuit. The variation detection circuit includes a reference filter having at least one resistor and at least one capacitor, detects a variation of CR-product based on the resistor and the capacitor of the reference filter in response to each of a plurality of reference signals having different frequencies from each other, and then outputs a variation detection signal indicating a detected result. The variation correction circuit corrects frequency characteristics of the main filter on the basis of the variation detection signal.
摘要翻译：滤波装置包括主滤波器，变化检测电路和变化校正电路。变化检测电路包括具有至少一个电阻器和至少一个电容器的参考滤波器，响应于具有不同频率的多个参考信号中的每一个，基于电阻器和参考滤波器的电容器检测CR乘积的变化然后输出指示检测结果的变化检测信号。变化校正电路根据变化检测信号校正主滤波器的频率特性。

3. 发明申请

US20070176682A1 Receiving circuit, and receiving apparatus and transmitting/receiving apparatus using the receiving circuit 失效
标题翻译：接收电路，以及使用接收电路的接收装置和发送/接收装置
公开(公告)号：US20070176682A1
公开(公告)日：2007-08-02
申请号：US10591850
申请日：2005-03-07
申请人： Makoto Nakamura , Hidehiko Kurimoto , Kaoru Ishida
发明人： Makoto Nakamura , Hidehiko Kurimoto , Kaoru Ishida
IPC分类号： H03G3/00
CPC分类号： H03G1/0088 , H03G3/3052 , H04B1/30
摘要： An object of the invention is to provide a receiving circuit where the quality of reception can be prevented from deteriorating when the gain changes, so that the good quality of the received signal can be preserved, as well as a receiving apparatus and a transmitting/receiving apparatus using the receiving circuit. In the configuration of the invention, a switch (113) is converted to a short state in response to a change in the gain of a variable gain amplifier (107) by means of a gain control apparatus 112, and thereby, the output terminal of a high pass filter (111) is fixed at a reference voltage and the cutoff frequency of a low pass filter (108) is increased. As a result, the period during which the DC voltage has transient response properties in the low pass filter (108) can be shortened, and this transient response prevented from passing through the high pass filter (111).
摘要翻译：本发明的目的是提供一种接收电路，其中当增益改变时可以防止接收质量恶化，从而可以保持接收信号的良好质量，以及接收装置和发送/接收使用接收电路的装置。在本发明的结构中，通过增益控制装置112响应于可变增益放大器（107）的增益的变化而将开关（113）转换为短状态，由此，输出端子高通滤波器（111）被固定在参考电压上，并且低通滤波器（108）的截止频率增加。结果，可以缩短在低通滤波器（108）中具有瞬态响应特性的直流电压的周期，并且防止该瞬态响应通过高通滤波器（111）。

4. 发明授权

US06559895B1 Analog memory and image processing system for reducing fixed pattern noise 有权
标题翻译：用于减少固定模式噪声的模拟记忆和图像处理系统
公开(公告)号：US06559895B1
公开(公告)日：2003-05-06
申请号：US09508447
申请日：2000-03-10
申请人： Shiro Dosho , Naoshi Yanagisawa , Masayuki Ozasa , Hidehiko Kurimoto , Tatsuo Okamoto
发明人： Shiro Dosho , Naoshi Yanagisawa , Masayuki Ozasa , Hidehiko Kurimoto , Tatsuo Okamoto
IPC分类号： H04N978
CPC分类号： G11C27/04 , G11C27/024
摘要： Fixed pattern noise of an analog memory is reduced. Transfer paths of an address selection signal (SL) between an address generation unit (10) and respective storage elements (21) for storing an analog signal are constructed to have a substantially uniform electric characteristic in driving the storage elements (21) by the address selection signal (SL) to such an extent that the output signal of the analog memory is free from fixed pattern noise. A buffer unit (50) for temporarily storing and outputting the address selection signal is provided between the address generation unit (10) and the respective storage elements (21), and the buffer unit (50) is constructed to have an output characteristic substantially uniform between the storage elements (21). Also, lines between the buffer unit (50) and the storage elements (21) are constructed to have substantially the same electric characteristic. In this manner, charge feed through noise of the respective storage elements (21) are made substantially uniform, resulting in suppressing the fixed pattern noise.
摘要翻译：模拟存储器的固定模式噪声降低。在地址产生单元（10）和用于存储模拟信号的各个存储元件（21）之间的地址选择信号（SL）的传输路径被构造为在通过地址驱动存储元件（21）时具有基本均匀的电特性选择信号（SL）使得模拟存储器的输出信号没有固定模式噪声的程度。用于临时存储和输出地址选择信号的缓冲单元（50）设置在地址生成单元（10）和各个存储元件（21）之间，缓冲单元（50）被构造成具有基本均匀的输出特性在所述存储元件（21）之间。此外，缓冲单元（50）和存储元件（21）之间的线被构造成具有基本上相同的电特性。以这种方式，通过各个存储元件（21）的噪声的电荷馈送被制成基本均匀，导致抑制固定图案噪声。

5. 发明授权

US06552402B1 Composite MOS transistor device 有权
标题翻译：复合MOS晶体管器件
公开(公告)号：US06552402B1
公开(公告)日：2003-04-22
申请号：US09287310
申请日：1999-04-07
申请人： Masayuki Ozasa , Tatsuo Okamoto , Hidehiko Kurimoto , Shiro Dosho , Kazuhiko Nagaoka
发明人： Masayuki Ozasa , Tatsuo Okamoto , Hidehiko Kurimoto , Shiro Dosho , Kazuhiko Nagaoka
IPC分类号： H01L2976
CPC分类号： H01L21/823456 , H01L27/088
摘要： A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated. Accordingly, in forming a differential amplifier or a current mirror circuit using this MOS transistor pair, high current gain can be obtained while maintaining an adequate balance in output current.
摘要翻译：用于半导体集成电路的复合MOS晶体管器件至少包括一对放置在同一板上的MOS晶体管或第一和第二MOS晶体管。第一和第二MOS晶体管分别由具有相等栅极宽度的等分分割晶体管组成。这些分离的晶体管在栅极纵向方向上彼此平行地布置。这些组的分割晶体管被布置成使得从中心线测量的各个栅极的坐标之和在栅极纵向方向上在这些组之间相等。由于各组栅极沿其长度的误差之和在每组分割晶体管中变为零，所以可以消除两个MOS晶体管之间的电流差。因此，在形成使用该MOS晶体管对的差分放大器或电流镜电路时，可以在保持输出电流的充分平衡的同时获得高电流增益。

6. 发明授权

US07454186B2 Direct conversion receiving apparatus and celluar phone 有权
标题翻译：直接转换接收设备和电话机
公开(公告)号：US07454186B2
公开(公告)日：2008-11-18
申请号：US11169978
申请日：2005-06-29
申请人： Takuji Yoneda , Hidehiko Kurimoto , Kaoru Ishida
发明人： Takuji Yoneda , Hidehiko Kurimoto , Kaoru Ishida
IPC分类号： H04B1/26
CPC分类号： H03G3/3078 , H03G1/04 , H03G3/3052 , H04B1/30
摘要： The direct conversion receiving apparatus has a gain control amplifier for variably amplifying a base band signal based on a gain switching control signal. A high pass filter has a first circuit including capacitors connected in parallel that are inserted in a path connecting an input terminal to an output terminal and switching effective total capacitance of the capacitors based on a first time constant switching control signal, and a second circuit including a resistor for providing a predetermined direct current voltage to the output terminal and switching the effective resistance value of the resistor based on a second time constant switching control signal. A control circuit outputs the gain switching control signal, and the first and second time constant switching control signals according to the change of the gain control of said gain control amplifier.
摘要翻译：直接变换接收装置具有用于基于增益切换控制信号可变地放大基带信号的增益控制放大器。高通滤波器具有第一电路，其包括并联连接的电容器，其插入到连接输入端子到输出端子的路径中，并且基于第一时间常数切换控制信号切换电容器的有效总电容;以及第二电路，包括用于向输出端子提供预定的直流电压并基于第二时间常数切换控制信号切换电阻器的有效电阻值的电阻器。控制电路根据所述增益控制放大器的增益控制的变化来输出增益切换控制信号以及第一和第二时间常数切换控制信号。

7. 发明申请

US20080139163A1 SEMICONDUCTOR CIRCUIT FOR WIRELESS RECEIVING PROVIDED WITH CONTROLLER CIRCUIT FOR CONTROLLING BIAS CURRENT 有权
标题翻译：用于控制电路的无线接收的半导体电路用于控制偏置电流
公开(公告)号：US20080139163A1
公开(公告)日：2008-06-12
申请号：US11951071
申请日：2007-12-05
申请人： Yasuo Oba , Hidehiko Kurimoto
发明人： Yasuo Oba , Hidehiko Kurimoto
IPC分类号： H04B1/16
CPC分类号： H04B1/28 , H04B1/18
摘要： A constant voltage source supplies a bias current to a wireless receiver circuit. A bias current detector circuit detects the bias current, and outputs a detection result to a current controller circuit. The current controller circuit outputs the detection result of the bias current to a memory circuit. The current controller circuit controls the bias current detector circuit to stop operating thereof, and then controls the bias current to decrease when the detected bias current is larger than a predetermined first threshold value and controls the bias current to increase when the detected bias current is smaller than a second threshold value smaller than the first threshold value, based on the detection result stored in the memory circuit.
摘要翻译：恒定电压源向无线接收器电路提供偏置电流。偏置电流检测器电路检测偏置电流，并将检测结果输出到电流控制器电路。电流控制器电路将偏置电流的检测结果输出到存储电路。电流控制器电路控制偏置电流检测器电路以停止其工作，然后当检测到的偏置电流大于预定的第一阈值时控制偏置电流减小，并且当检测到的偏置电流较小时控制偏置电流增加比基于存储在存储器电路中的检测结果小于第一阈值的第二阈值。

8. 发明授权

US07376405B2 Receiver circuit 失效
标题翻译：接收电路
公开(公告)号：US07376405B2
公开(公告)日：2008-05-20
申请号：US11041868
申请日：2005-01-25
申请人： Hidehiko Kurimoto , Makoto Nakamura , Tomonori Nakajima
发明人： Hidehiko Kurimoto , Makoto Nakamura , Tomonori Nakajima
IPC分类号： H04B1/00
CPC分类号： H04B1/1615 , H04B1/30 , H04W52/028 , Y02D70/40
摘要： Interruption of a reception signal is achieved by placing a first low noise amplifier into the sleep state, and short-circuiting a shunt switch provided between differential input terminals of a second low noise amplifier during a DC offset canceling period. Further, an antenna switch is switched to a circuit system where DC offset canceling is not performed for preventing the input of the reception signal to a circuit system where DC offset canceling is performed.
摘要翻译：接收信号的中断通过将第一低噪声放大器置于睡眠状态，并且在DC偏移消除周期期间使设置在第二低噪声放大器的差分输入端之间的分流开关短路来实现。此外，天线开关切换到电路系统，其中不执行DC偏移抵消以防止将接收信号输入到执行DC偏移消除的电路系统。

9. 发明申请

US20060009182A1 Direct conversion receiving apparatus and cellular phone 有权
标题翻译：直接转换接收设备和手机
公开(公告)号：US20060009182A1
公开(公告)日：2006-01-12
申请号：US11169978
申请日：2005-06-29
申请人： Takuji Yoneda , Hidehiko Kurimoto , Kaoru Ishida
发明人： Takuji Yoneda , Hidehiko Kurimoto , Kaoru Ishida
IPC分类号： H04B1/06 , H04L27/08 , H04B7/00
CPC分类号： H03G3/3078 , H03G1/04 , H03G3/3052 , H04B1/30
摘要： The direct conversion receiving apparatus has a gain control amplifier for variably amplifying a base band signal based on a gain switching control signal. A high pass filter has a first circuit including capacitors connected in parallel that are inserted in a path connecting an input terminal to an output terminal and switching effective total capacitance of the capacitors based on a first time constant switching control signal, and a second circuit including a resistor for providing a predetermined direct current voltage to the output terminal and switching the effective resistance value of the resistor based on a second time constant switching control signal. A control circuit outputs the gain switching control signal, and the first and second time constant switching control signals according to the change of the gain control of said gain control amplifier.
摘要翻译：直接变换接收装置具有用于基于增益切换控制信号可变地放大基带信号的增益控制放大器。高通滤波器具有第一电路，其包括并联连接的电容器，其插入到连接输入端子到输出端子的路径中，并且基于第一时间常数切换控制信号切换电容器的有效总电容;以及第二电路，包括用于向输出端子提供预定的直流电压并基于第二时间常数切换控制信号切换电阻器的有效电阻值的电阻器。控制电路根据所述增益控制放大器的增益控制的变化来输出增益切换控制信号以及第一和第二时间常数切换控制信号。

10. 发明授权

US07801503B2 Direct conversion receiver circuit 有权
标题翻译：直接转换接收电路
公开(公告)号：US07801503B2
公开(公告)日：2010-09-21
申请号：US11400936
申请日：2006-04-10
申请人： Hidehiko Kurimoto
发明人： Hidehiko Kurimoto
IPC分类号： H04B1/06
CPC分类号： H03D3/008
摘要： A receiver circuit includes a low noise amplifier (LNA) 1 to which a received signal is input, a mixer 2 for mixing an output of the LNA and a local signal, a first low-pass filter 3 for receiving an output of the mixer, and a composite amplifier in which a fixed gain amplifier 4, a high-pass filter 5, and a gain control amplifier 6 are connected in this order from the input side. An output of the first low-pass filter is input to the fixed gain amplifier. The gain of the fixed gain amplifier is 0 dB or more. The maximum gain of the gain control amplifier is 0 dB or less. The receiver circuit can suppress a transient response due to DC voltage fluctuations, even if the gains are changed while signals are received in a communication mode that performs continuous reception.
摘要翻译：接收机电路包括：输入接收信号的低噪声放大器（LNA）1，用于混合LNA的输出的混合器2和本地信号;接收混频器的输出的第一低通滤波器3，以及其中固定增益放大器4，高通滤波器5和增益控制放大器6从输入侧依次连接的复合放大器。第一低通滤波器的输出被输入到固定增益放大器。固定增益放大器的增益为0 dB以上。增益控制放大器的最大增益为0 dB或更小。即使在以连续接收的通信方式接收信号的同时，接收电路也可以抑制由于直流电压波动引起的瞬态响应。

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