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11. 发明授权

US4742018A Process for producing memory cell having stacked capacitor 失效
标题翻译：具有层叠电容器的存储单元的制造方法
公开(公告)号：US4742018A
公开(公告)日：1988-05-03
申请号：US936602
申请日：1986-12-01
申请人： Shinichiro Kimura , Hideo Sunami
发明人： Shinichiro Kimura , Hideo Sunami
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87 , Y10S148/014
摘要： A process for producing a memory cell having a stacked capacitor. As the reduction in device size of memory cells progresses, it becomes difficult to obtain a satisfactorily large capacitance even with a stacked capacitor structure. To enable a larger capacitance to be obtained for the same occupied area, projections and recesses are provided on the surface of a capacitor electrode. It is possible, according to the process, to readily produce projections and recesses for increasing the storage capacitance.
摘要翻译：一种具有叠层电容器的存储单元的制造方法。随着存储器单元的器件尺寸的减小进行，即使堆叠的电容器结构也难以获得令人满意的大电容。为了能够为相同的占用面积获得更大的电容，在电容器电极的表面上设置有凹凸。根据该方法，可以容易地产生用于增加存储电容的凸起和凹槽。

12. 发明授权

US4670768A Complementary MOS integrated circuits having vertical channel FETs 失效
标题翻译：具有垂直沟道FET的互补MOS集成电路
公开(公告)号：US4670768A
公开(公告)日：1987-06-02
申请号：US767794
申请日：1985-08-14
申请人： Hideo Sunami , Makoto Ohkura , Shinichiro Kimura
发明人： Hideo Sunami , Makoto Ohkura , Shinichiro Kimura
IPC分类号： H01L27/08 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786 , H01L27/02 , H01L27/12 , H01L29/06
CPC分类号： H01L29/7827 , H01L21/8221 , H01L21/823885 , H01L27/0688 , H01L27/092 , H01L27/1104 , H01L29/78642
摘要： A semiconductor integrated circuit comprising semiconductor regions in the form of first and second protruding poles that are provided on a semiconductor layer formed on a semiconductor substrate or an insulating substrate, and that are opposed to each other with an insulating region sandwiched therebetween, a p-channel FET provided in the first semiconductor region, and an n-channel FET provided in the second semiconductor region. These FET's have source and drain regions on the upper and bottom portions of the semiconductor regions, and have gate electrodes on the sides of the semiconductor regions. The insulation region between the protruding pole-like semiconductor regions is further utilized as the gate electrode and the gate insulating film.
摘要翻译： PCT No.PCT / JP84 / 00597 Sec。 371日期1985年8月14日 102（e）日期1985年8月14日PCT提交1984年12月14日PCT公布。第WO85 / 02716号公报日期：1985年6月20日。一种半导体集成电路，包括第一和第二突出极的形式的半导体区域，所述半导体区域设置在形成在半导体衬底或绝缘衬底上的半导体层上，并且具有绝缘设置在第一半导体区域中的p沟道FET，以及设置在第二半导体区域中的n沟道FET。这些FET在半导体区域的上部和底部具有源极和漏极区域，并且在半导体区域的侧面上具有栅极电极。突出的柱状半导体区域之间的绝缘区域被进一步用作栅极电极和栅极绝缘膜。

13. 发明授权

US5346834A Method for manufacturing a semiconductor device and a semiconductor memory device 失效
标题翻译：半导体装置及半导体存储装置的制造方法
公开(公告)号：US5346834A
公开(公告)日：1994-09-13
申请号：US845063
申请日：1992-03-03
申请人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
发明人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
IPC分类号： H01L21/336 , H01L21/339 , H01L21/762 , H01L21/8238 , H01L21/8242 , H01L21/8248 , H01L21/8249 , H01L27/108 , H01L27/11 , H01L29/10 , H01L29/423 , H01L29/786 , H01L21/265
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/10808 , H01L27/10852 , H01L27/10873 , H01L27/1108 , H01L29/1062 , H01L29/42384 , H01L29/66772 , H01L29/66795 , H01L29/66954 , H01L29/78654 , H01L21/76278 , Y10S148/014
摘要： An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.
摘要翻译：提供了一种用于制造绝缘栅场效应晶体管的改进方法。作为第一步骤，在硅衬底上生长氧化硅膜，并且在其上沉积第一氮化硅膜。然后使用抗蚀剂图案作为掩模来蚀刻第一硅亚硝酸盐膜，氧化硅膜和硅衬底，以形成包括硅衬底的至少一部分的硅岛。然后在通过第二步骤暴露的硅衬底的表面上以及在硅岛的表面上生长第二氧化硅膜，并且在其上沉积第二硅亚硝酸盐膜。然后蚀刻第二硅亚硝酸盐膜以留下沉积在硅岛的侧壁上的第二硅亚硝酸盐膜的一部分。之后，通过硅衬底的表面的热氧化生长第三氧化硅膜，以将硅岛与硅衬底电隔离。接下来，在硅岛上形成栅电极，随后在硅岛中形成源极和漏极区域，采用栅电极作为掩模。

14. 发明授权

US5115289A Semiconductor device and semiconductor memory device 失效
标题翻译：半导体器件和半导体存储器件
公开(公告)号：US5115289A
公开(公告)日：1992-05-19
申请号：US742196
申请日：1991-08-05
申请人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
发明人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
IPC分类号： H01L21/336 , H01L21/339 , H01L21/762 , H01L21/8238 , H01L21/8242 , H01L21/8248 , H01L21/8249 , H01L27/108 , H01L27/11 , H01L29/10 , H01L29/423 , H01L29/786
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/10808 , H01L27/10826 , H01L27/10852 , H01L27/10873 , H01L27/10879 , H01L27/1108 , H01L29/1062 , H01L29/42384 , H01L29/66772 , H01L29/66795 , H01L29/66954 , H01L29/78654 , H01L21/76278
摘要： A semiconductor device, such as an FET or a charge coupled device, is provided having a channel or a charge coupled portion formed in a thin semiconductor layer which is substantially perpendicular to the substrate. Necessary electrodes, such as the gate electrode, and necessary insulating layers can be added at the thin semiconductor layer, and can maintain the necessary amount of electric current by securing the height of the semiconductor layer. The structure has the advantage that it can have its plane size reduced. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.
摘要翻译：提供了诸如FET或电荷耦合器件的半导体器件，其具有形成在基本上垂直于衬底的薄半导体层中的沟道或电荷耦合部分。可以在薄的半导体层添加必要的电极，例如栅电极和必要的绝缘层，并且可以通过确保半导体层的高度来保持必要的电流量。该结构具有能够减小其平面尺寸的优点。此外，使用上述半导体器件的半导体存储器件适合于高集成度并且具有优异的电特性。

15. 发明授权

US4970564A Semiconductor memory device having stacked capacitor cells 失效
标题翻译：具有层叠电容器单元的半导体存储器件
公开(公告)号：US4970564A
公开(公告)日：1990-11-13
申请号：US287881
申请日：1988-12-21
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10808
摘要： A semiconductor memory device having STC cells wherein major portions of active regions consisting of channel-forming portions are tilted at an angle of 45.degree. with respect to the word lines and the bit lines that meet at right angles with each other, enabling the storage capacity portions to be arranged very densely and sufficiently large capacities to be maintained with very small cell areas. In the semiconductor memory device, furthermore, the storage capacity portions are formed even on the bit lines. Therefore, the bit lines are shielded, the capacitance between the bit lines decreases, and the memory array noise decreases.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45°的角度倾斜，使得存储容量部分布置得非常密集和足够大的容量保持非常小的单元格区域。此外，在半导体存储器件中，即使在位线上形成存储容量部分。因此，位线被屏蔽，位线之间的电容减小，并且存储器阵列噪声降低。

16. 发明授权

US5466621A Method of manufacturing a semiconductor device having silicon islands 失效
标题翻译：制造具有硅岛的半导体器件的方法
公开(公告)号：US5466621A
公开(公告)日：1995-11-14
申请号：US141027
申请日：1993-10-25
申请人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
发明人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
IPC分类号： H01L21/336 , H01L21/339 , H01L21/762 , H01L21/8238 , H01L21/8242 , H01L21/8248 , H01L21/8249 , H01L27/108 , H01L27/11 , H01L29/10 , H01L29/423 , H01L29/786 , H01L21/70 , H01L27/00
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/10808 , H01L27/10852 , H01L27/10873 , H01L27/1108 , H01L29/1062 , H01L29/42384 , H01L29/66772 , H01L29/66795 , H01L29/66954 , H01L29/78654 , H01L21/76278 , Y10S148/014
摘要： A semiconductor device such as FET or charge coupled device, having a channel or a charge coupled portion provided in a thin semiconductor layer which is nearly perpendicular to the substrate and to which the necessary electrode such as the gate electrode and the necessary insulating layer are added can maintain the necessary amount of electric current by securing the height of the semiconductor layer and also can have its plane size reduced minutely. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.
摘要翻译：一种诸如FET或电荷耦合器件的半导体器件，其具有设置在薄半导体层中的沟道或电荷耦合部分，该半导体层几乎垂直于衬底并且添加诸如栅电极和必需绝缘层的必需电极可以通过确保半导体层的高度来保持必要的电流量，并且还可以使其平面尺寸微小地减小。此外，使用上述半导体器件的半导体存储器件适合于高集成度并且具有优异的电特性。

17. 发明申请

US20100232231A1 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US20100232231A1
公开(公告)日：2010-09-16
申请号：US12787158
申请日：2010-05-25
申请人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

18. 发明申请

US20100135080A1 FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US20100135080A1
公开(公告)日：2010-06-03
申请号：US12648796
申请日：2009-12-29
申请人： Digh HISAMOTO , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
发明人： Digh HISAMOTO , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

19. 发明申请

US20100097246A1 INPUT DEVICE AND KEYBOARD DEVICE HAVING ILLUMINATION FUNCTION 失效
标题翻译：具有照明功能的输入设备和键盘设备
公开(公告)号：US20100097246A1
公开(公告)日：2010-04-22
申请号：US12579903
申请日：2009-10-15
申请人： Kazutoshi WATANABE , Hideaki Nagakubo , Takenobu Kimura , Koichi Yamamoto , Katsuyki Katayama , Naomi Sato , Naoya Akiyama , Shinichiro Kimura , Masahiro Ishida , Naoki Yamada , Keiji Takagi , Toshinobu Hosaka
发明人： Kazutoshi WATANABE , Hideaki Nagakubo , Takenobu Kimura , Koichi Yamamoto , Katsuyki Katayama , Naomi Sato , Naoya Akiyama , Shinichiro Kimura , Masahiro Ishida , Naoki Yamada , Keiji Takagi , Toshinobu Hosaka
IPC分类号： H03M11/00
CPC分类号： G06F3/0202 , H01H13/83 , H01H2219/044 , H01H2219/056 , H01H2219/06 , H01H2219/062
摘要： An input device includes a plurality of manipulation portions; an input function portion manipulated by the manipulation portions to perform an input function; a light guiding sheet facing the rear side of the plurality of manipulation portions; and a light source applying light into the light guiding sheet, wherein a rear surface opposite to a front surface of the light guiding sheet facing the manipulation portions is provided with a plurality of concave portions which is depressed to the inside of the light guiding sheet, wherein each concave portion has a circular opening and an inner surface which is a smooth concave curve surface, and wherein light propagated through the inside of the light guiding sheet is reflected by the inner surface toward the inside of the light guiding sheet, and the light is applied from the front surface of the light guiding sheet to the manipulation portions.
摘要翻译：输入装置包括多个操作部分; 由操作部分操纵以输入功能的输入功能部分; 面向所述多个操作部的后侧的导光片; 以及向所述导光片施加光的光源，其中与所述导光片的面对所述操作部的前表面相对的后表面设置有多个凹陷部，所述凹部被压向所述导光片的内部，其特征在于，每个凹部具有圆形开口和内表面，该内表面是光滑的凹曲面，并且其中通过导光片的内部传播的光被内表面朝向导光片的内部反射，并且光从导光片的前表面施加到操作部。

20. 发明申请

US20100084709A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100084709A1
公开(公告)日：2010-04-08
申请号：US11993862
申请日：2006-06-30
申请人： Ryuta Tsuchiya , Shinichiro Kimura
发明人： Ryuta Tsuchiya , Shinichiro Kimura
IPC分类号： H01L29/786 , H01L21/336 , H01L21/86
CPC分类号： H01L27/12 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1207
摘要： When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced. A simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.
摘要翻译：当单独使用体硅衬底和SOI衬底时，板面积增加，因此整体上不可能减小半导体器件的尺寸。另一方面，当在同一衬底上形成SOI型MISFET和体型MISFET时，分别将SOI型MISFET和体型MISFET分别形成，因此工艺变得复杂。使用通过薄埋入绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的单晶半导体衬底和SOI衬底，以及良好扩散层区域，漏极区域，栅极绝缘膜并且以相同的步骤形成SOI型MISFET和体型MISFET的栅电极。由于可以在同一基板上形成体型MISFET和SOI型MISFET，所以可以减小电路板面积。可以通过制造SOI型MISFET和体型MISFET的制造步骤来实现简单的工艺。

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