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11. 发明申请

US20060183296A1 Isolation method for semiconductor device 审中-公开
公开(公告)号：US20060183296A1
公开(公告)日：2006-08-17
申请号：US11398536
申请日：2006-04-06
申请人： Jae-yoon Yoo , Moon-han Park , Dong-ho Ahn , Sug-hun Hong , Kyung-won Park , Jeong-soo Lee
发明人： Jae-yoon Yoo , Moon-han Park , Dong-ho Ahn , Sug-hun Hong , Kyung-won Park , Jeong-soo Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： An isolation method for a semiconductor device where an insulating mask layer is formed on desired regions of a semiconductor substrate. A trench is formed to a desired depth in the semiconductor substrate using the insulating mask layer as a mask. An oxide layer is formed on the insulating mask layer and on the sidewall of the trench. A trench liner layer is formed on the oxide layer. An insulating filler layer is formed in the trench in the semiconductor substrate, on which the trench liner layer is formed, so as to fill the trench. The insulating mask layer is removed. According to the isolation method for a semiconductor device, it is possible to reduce dents from occurring along the edge of the trench, reduce a bird's beak type oxide layer from occurring at an interface between the insulating mask layers, decrease the leakage current, or improve the electrical characteristics, such as threshold voltage.

12. 发明授权

US06835621B2 Method of fabricating non-volatile memory device having a structure of silicon-oxide-nitride-oxide-silicon 有权
标题翻译：制造具有氧化硅 - 氮化物 - 氧化物 - 硅的结构的非易失性存储器件的方法
公开(公告)号：US06835621B2
公开(公告)日：2004-12-28
申请号：US10455676
申请日：2003-06-05
申请人： Jae-yoon Yoo , Moon-han Park , Dae-jin Kwon
发明人： Jae-yoon Yoo , Moon-han Park , Dae-jin Kwon
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L21/022 , H01L21/02238 , H01L21/02326 , H01L21/28282 , H01L21/3144 , H01L21/31612 , H01L21/32105 , H01L27/115 , H01L29/66833
摘要： In a method of fabricating a non-volatile memory device with a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a silicon nitride layer, which is a charge trapping layer, and a polysilicon layer, which is a control gate electrode, are electrically isolated from one another in the resulting structure. According to the method, a silicon oxide layer as a tunneling layer and a silicon nitride layer pattern as a charge trapping layer are formed on a semiconductor substrate; an oxidation process is performed to form a silicon nitride oxide layer, as a blocking layer, at top and sides of the silicon nitride layer pattern and to form a gate insulating layer at an exposed portion of the semiconductor substrate; and a control gate electrode is formed on the silicon nitride oxide layer and the gate insulating layer.
摘要翻译：在制造具有氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）结构的非易失性存储器件的方法中，作为电荷俘获层的氮化硅层和作为控制栅电极的多晶硅层在所得结构中彼此电隔离。根据该方法，在半导体衬底上形成作为隧穿层的氧化硅层和作为电荷俘获层的氮化硅层图案; 进行氧化处理以在氮化硅层图案的顶部和侧面形成氮化硅氧化物层作为阻挡层，并在半导体衬底的暴露部分形成栅极绝缘层; 并且在氮氧化硅层和栅极绝缘层上形成控制栅电极。

13. 发明授权

US06717231B2 Trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
标题翻译：沟槽隔离区域在其中具有防止过蚀刻的凹陷抑制层
公开(公告)号：US06717231B2
公开(公告)日：2004-04-06
申请号：US10224017
申请日：2002-08-20
申请人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
发明人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
摘要翻译：形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。掩模层可以包括氮化硅。然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。接下来，在凹陷抑制层上形成应力消除层。该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。然后用沟槽隔离层填充沟槽。然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

14. 发明授权

US06624041B2 Method for forming trench type isolation film using annealing 失效
标题翻译：使用退火形成沟槽型隔离膜的方法
公开(公告)号：US06624041B2
公开(公告)日：2003-09-23
申请号：US09316029
申请日：1999-05-21
申请人： Soo-jin Hong , Moon-han Park
发明人： Soo-jin Hong , Moon-han Park
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/823481
摘要： A method for forming a trench type isolation film comprises filling a trench with a composite film, flattening the resultant, and annealing the flattened resultant before a gate oxide film is formed. The annealing diffuses out any contaminant existing in an area near and/or contacting the trench on a surface between a semiconductor substrate and a pad oxide film. Therefore, it is possible to prevent the portion of the gate oxide film which is near the trench from becoming thinner than other portions. Accordingly, it is possible to prevent the characteristic of the gate oxide film from deteriorating. In particular, it is possible to prevent a break down voltage from being lowered.
摘要翻译：用于形成沟槽型隔离膜的方法包括用复合膜填充沟槽，使所得的产品平坦化，并且在形成栅极氧化膜之前使扁平化的结果退火。退火在半导体衬底和衬垫氧化物膜之间的表面上扩散存在于接近和/或接触沟槽的区域中的任何污染物。因此，可以防止沟槽附近的栅极氧化膜的部分变得比其他部分薄。因此，可以防止栅极氧化膜的特性劣化。特别地，可以防止分解电压降低。

15. 发明授权

US06482715B2 Method of forming shallow trench isolation layer in semiconductor device 有权
公开(公告)号：US06482715B2
公开(公告)日：2002-11-19
申请号：US09927340
申请日：2001-08-13
申请人： Tai-su Park , Ho-kyu Kang , Dong-ho Ahn , Moon-han Park
发明人： Tai-su Park , Ho-kyu Kang , Dong-ho Ahn , Moon-han Park
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

16. 发明授权

US5728620A Isolation method of semiconductor device 失效
标题翻译：半导体器件的隔离方法
公开(公告)号：US5728620A
公开(公告)日：1998-03-17
申请号：US591826
申请日：1996-01-25
申请人： Moon-han Park
发明人： Moon-han Park
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/76202
摘要： A device isolation method divides a semiconductor substrate into active and inactive regions. A first device isolation layer is formed in a first inactive region using a trench isolation method. Then, local oxidation is used to form a second device isolation layer in a second inactive region which is wider than the first. A dishing phenomenon (generated during CMP processing) is eliminated, and proper device isolation is realized without exposing the active region.
摘要翻译：器件隔离方法将半导体衬底划分成活性和非活性区域。使用沟槽隔离方法在第一非活性区域中形成第一器件隔离层。然后，使用局部氧化在第二非活性区域中形成第二器件隔离层，其比第一非区域宽。消除了凹陷现象（在CMP处理期间产生），并且在不暴露有源区的情况下实现适当的器件隔离。

17. 发明授权

US08877579B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08877579B2
公开(公告)日：2014-11-04
申请号：US13417787
申请日：2012-03-12
申请人： Moon-kyun Song , Ha-jin Lim , Moon-han Park , Jin-ho Do
发明人： Moon-kyun Song , Ha-jin Lim , Moon-han Park , Jin-ho Do
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/823807
摘要： Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.
摘要翻译：制造半导体器件的方法包括提供包括NMOS区域和PMOS区域的衬底，将氟离子注入到衬底的上表面中，形成NMOS区域的第一栅极电极和衬底上的PMOS区域的第二栅极电极在所述基板的与所述第一栅电极和所述第二栅电极的两个侧面相邻的部分分别形成源极区域和漏极区域，并在所述第一栅极电极和所述第二栅极电极的上表面上进行高压热处理工序通过使用非氧化性气体的基板。

18. 发明授权

US06461937B1 Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
标题翻译：形成其中具有防止过蚀刻的凹陷抑制层的沟槽隔离区的方法
公开(公告)号：US06461937B1
公开(公告)日：2002-10-08
申请号：US09479442
申请日：2000-01-07
申请人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
发明人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
摘要翻译：形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。掩模层可以包括氮化硅。然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。接下来，在凹陷抑制层上形成应力消除层。该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。然后用沟槽隔离层填充沟槽。然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

19. 发明申请

US20120309144A1 METHODS OF FORMING MOSFET DEVICES USING NITROGEN-INJECTED OXIDE LAYERS TO FORM GATE INSULATING LAYERS HAVING DIFFERENT THICKNESSES 有权
标题翻译：使用氮注入氧化物层形成具有不同厚度的栅绝缘层的MOSFET器件的方法
公开(公告)号：US20120309144A1
公开(公告)日：2012-12-06
申请号：US13480947
申请日：2012-05-25
申请人： Jin-ho Do , Moon-han Park , Weon-hong Kim , Kyung-il Hong
发明人： Jin-ho Do , Moon-han Park , Weon-hong Kim , Kyung-il Hong
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L21/823857 , H01L21/28202 , H01L29/518
摘要： In some embodiments of the inventive subject matter, methods include forming an oxide layer on a semiconductor substrate, injecting nitrogen into the oxide layer to form a nitrogen injection layer and to change the oxide layer to an oxynitride layer, removing a part of the oxynitride layer to leave a portion of the oxynitride layer in a first area and expose the nitrogen injection layer in a second area and forming an insulating layer comprising a portion on the portion of the oxynitride layer in the first area and a portion on the nitrogen injection layer in the second area. The insulating layer may have a higher dielectric constant than the oxide layer.
摘要翻译：在本发明的一些实施方案中，方法包括在半导体衬底上形成氧化物层，将氮注入到氧化物层中以形成氮注入层并将氧化物层改变为氧氮化物层，去除一部分氮氧化物层将氮氧化物层的一部分留在第一区域中，并在第二区域中露出氮气注入层，并形成绝缘层，该绝缘层包括第一区域中的氧氮化物层的一部分和氮注入层上的部分第二个区域。绝缘层可以具有比氧化物层更高的介电常数。

20. 发明授权

US5885883A Methods of forming trench-based isolation regions with reduced susceptibility to edge defects 失效
标题翻译：形成具有降低的边缘缺陷敏感性的基于沟槽的隔离区域的方法
公开(公告)号：US5885883A
公开(公告)日：1999-03-23
申请号：US834245
申请日：1997-04-15
申请人： Moon-han Park , Yu-gyun Shin
发明人： Moon-han Park , Yu-gyun Shin
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232
摘要： Methods of forming trench-based isolation regions with reduced susceptibility to edge defects include the steps of forming trenches at a face of a semiconductor substrate and then filling the trenches with electrically insulating regions. However, to prevent exposure of those portions of the substrate extending adjacent the trenches, supplemental oxide regions are formed at the interfaces between the upper portions of the trench sidewalls and the electrically insulating regions in the trenches, by exposing the electrically insulating regions to an oxidation atmosphere at a temperature in a range between about 950.degree. C. and 1100.degree. C. In particular, the supplemental oxide regions are formed as thermal oxides of higher density than the electrically insulating regions in the trenches. Thus, the supplemental oxide regions are more resistant to chemical etchants. Accordingly, when the electrically insulating regions are planarized and etched during back end processing steps, the supplemental oxide regions will not be entirely etched and, therefore, those portions of the substrate (i.e., active regions) extending adjacent the trenches will not be exposed.
摘要翻译：形成具有降低的边缘缺陷敏感性的沟槽隔离区的方法包括以下步骤：在半导体衬底的表面形成沟槽，然后用电绝缘区填充沟槽。然而，为了防止邻近沟槽延伸的衬底的那些部分的暴露，在沟槽侧壁的上部和沟槽中的电绝缘区域之间的界面处，通过将电绝缘区域暴露于氧化物形成辅助氧化物区域在约950℃至1100℃的温度范围内的气氛。特别地，补充氧化物区域形成为比沟槽中的电绝缘区域更高密度的热氧化物。因此，补充氧化物区域更耐化学蚀刻剂。因此，当在后端处理步骤中对电绝缘区域进行平面化和蚀刻时，补充氧化物区域将不会被完全蚀刻，因此，邻近沟槽延伸的衬底（即，有源区域）的那些部分将不被暴露。

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