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11. 发明授权

US07243274B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07243274B2
公开(公告)日：2007-07-10
申请号：US11206170
申请日：2005-08-18
申请人： Masafumi Yamazaki , Takaaki Suzuki , Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo , Ayako Sato , Takayuki Yoneda , Noriko Kawamura
发明人： Masafumi Yamazaki , Takaaki Suzuki , Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo , Ayako Sato , Takayuki Yoneda , Noriko Kawamura
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/36
摘要： An external terminal receives an external signal so as to access the first and second memory chips. The test starting terminal receives a test starting signal activated when the first or second memory chip is tested and inactivated when the first and second memory chips are normally operated. The access signal generator converts the external signal to a memory access signal of the first memory chip. The first selector selects the external signal, which is a test signal, during activation of the test starting signal, selects the memory access signal during the inactivation of the test starting signal. That is, during the test modes, the first memory chip can be directly accessed from the exterior. For this reason, the test program for testing the first memory chip alone can be diverted as the test program following an assembly of the semiconductor device.
摘要翻译：外部终端接收外部信号以访问第一和第二存储器芯片。当第一和第二存储器芯片正常工作时，测试启动终端接收到测试启动信号，当第一或第二存储器芯片被测试和非激活时激活。访问信号发生器将外部信号转换为第一存储器芯片的存储器访问信号。第一选择器在激活测试启动信号期间选择作为测试信号的外部信号，在测试启动信号失效期间选择存储器访问信号。也就是说，在测试模式期间，可以从外部直接访问第一存储器芯片。因此，在半导体器件的组装之后，用于单独测试第一存储器芯片的测试程序可以作为测试程序转移。

12. 发明申请

US20050052935A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20050052935A1
公开(公告)日：2005-03-10
申请号：US10968072
申请日：2004-10-20
申请人： Toshiya Miyo , Toshikazu Nakamura , Satoshi Eto
发明人： Toshiya Miyo , Toshikazu Nakamura , Satoshi Eto
IPC分类号： G11C11/4097 , G11C8/00
CPC分类号： G11C11/4097
摘要： Second memory cells of a second memory block each have an area 2a times (a is a positive integer) that of each first memory cell of a first memory block. Sizing the first and second memory cells in a predetermined ratio can make easily identical the dimensions of the first memory block and the second memory block. Consequently, it is possible to easily align peripheral circuits to lie around the plurality of first and second memory blocks, such as decoders. This also facilitates the wiring of signal lines to be connected to the peripheral circuits. This makes it possible to improve the layout design efficiency for a semiconductor integrated circuit. Thus, a plurality of types of memory blocks can be formed on a semiconductor integrated circuit efficiently. The semiconductor integrated circuit can be prevented from increasing in chip size depending on the layout design, owing to its simplified layout.
摘要翻译：第二存储器块的第二存储器单元各自具有第一存储器块的每个第一存储器单元的区域2。以预定比例对第一和第二存储器单元进行尺寸可以使得第一存储块和第二存储块的尺寸容易相同。因此，可以容易地将外围电路对准在诸如解码器之类的多个第一和第二存储器块周围。这也有助于连接到外围电路的信号线的布线。这使得可以提高半导体集成电路的布局设计效率。因此，可以有效地在半导体集成电路上形成多种类型的存储块。由于布局简单，可以防止半导体集成电路因布局设计而增加芯片尺寸。

13. 发明授权

US07193922B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07193922B2
公开(公告)日：2007-03-20
申请号：US10968072
申请日：2004-10-20
申请人： Toshiya Miyo , Toshikazu Nakamura , Satoshi Eto
发明人： Toshiya Miyo , Toshikazu Nakamura , Satoshi Eto
IPC分类号： G11C8/00 , G11C5/06
CPC分类号： G11C11/4097
摘要： Second memory cells of a second memory block each have an area 2a times (a is a positive integer) that of each first memory cell of a first memory block. Sizing the first and second memory cells in a predetermined ratio can make easily identical the dimensions of the first memory block and the second memory block. Consequently, it is possible to easily align peripheral circuits to lie around the plurality of first and second memory blocks, such as decoders. This also facilitates the wiring of signal lines to be connected to the peripheral circuits. This makes it possible to improve the layout design efficiency for a semiconductor integrated circuit. Thus, a plurality of types of memory blocks can be formed on a semiconductor integrated circuit efficiently. The semiconductor integrated circuit can be prevented from increasing in chip size depending on the layout design, owing to its simplified layout.
摘要翻译：第二存储器块的第二存储单元分别具有第一存储器块的每个第一存储器单元的区域2（a）为正整数）。以预定比例对第一和第二存储器单元进行尺寸可以使得第一存储块和第二存储块的尺寸容易相同。因此，可以容易地将外围电路对准在诸如解码器之类的多个第一和第二存储器块周围。这也有助于连接到外围电路的信号线的布线。这使得可以提高半导体集成电路的布局设计效率。因此，可以有效地在半导体集成电路上形成多种类型的存储块。由于布局简单，可以防止半导体集成电路因布局设计而增加芯片尺寸。

14. 发明申请

US20060023547A1 Semiconductor memory 失效
公开(公告)号：US20060023547A1
公开(公告)日：2006-02-02
申请号：US11215045
申请日：2005-08-31
申请人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
发明人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C7/22 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/2281 , G11C2211/4061
摘要： A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.

15. 发明申请

US20060015788A1 Semiconductor device 有权
公开(公告)号：US20060015788A1
公开(公告)日：2006-01-19
申请号：US11206170
申请日：2005-08-18
申请人： Masafumi Yamazaki , Takaaki Suzuki , Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo , Ayako Sato , Takayuki Yoneda , Noriko Kawamura
发明人： Masafumi Yamazaki , Takaaki Suzuki , Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo , Ayako Sato , Takayuki Yoneda , Noriko Kawamura
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/48 , G11C29/36
摘要： A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern(s) for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern(s) outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern(s) (the first test mode) generated within the logic chip or the external test pattern (the second test mode) supplied from the exterior.

16. 发明授权

US06961881B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06961881B2
公开(公告)日：2005-11-01
申请号：US10122181
申请日：2002-04-16
申请人： Masafumi Yamazaki , Takaaki Suzuki , Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo , Ayako Sato , Takayuki Yoneda , Noriko Kawamura
发明人： Masafumi Yamazaki , Takaaki Suzuki , Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo , Ayako Sato , Takayuki Yoneda , Noriko Kawamura
IPC分类号： G11C29/00 , G11C29/36 , G11C29/48
CPC分类号： G11C29/48 , G11C29/36
摘要： A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern in the first test mode, generated within the logic chip, or the external test pattern in the second test mode, supplied from the exterior.
摘要翻译：由逻辑芯片访问的逻辑芯片和存储器芯片安装在单个封装中。逻辑芯片的模式发生器在第一测试模式下操作以产生用于存储器芯片的内部测试模式。模式选择器在第一测试模式期间选择从模式发生器输出的内部测试模式，在第二测试模式期间，选择通过测试终端提供的外部测试模式，并将所选择的测试模式输出到存储芯片。通过使用模式选择信号，在第二测试模式中使用在逻辑芯片内产生的第一测试模式中的内部测试模式或外部测试模式来测试安装在封装中的存储芯片，从外部。

17. 发明授权

US06819610B2 DRAM operating like SRAM 失效
标题翻译： DRAM像SRAM一样运行
公开(公告)号：US06819610B2
公开(公告)日：2004-11-16
申请号：US10267873
申请日：2002-10-10
申请人： Toshiya Miyo , Toshikazu Nakamura , Satoshi Eto , Ayako Sato , Masato Matsumiya
发明人： Toshiya Miyo , Toshikazu Nakamura , Satoshi Eto , Ayako Sato , Masato Matsumiya
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C11/4094
摘要： A semiconductor memory device includes a first bit line connected to a memory cell via a transistor, a transfer gate, a second bit line connected to the first bit line via the transfer gate, a sense amplifier connected to the second bit line, a first precharge circuit for precharging the first bit line, a second precharge circuit for precharging the second bit line, a control circuit which precharges the first bit line by the first precharge circuit after closing the transfer gate, followed by subsequent precharging of the second bit line by the second precharge circuit.
摘要翻译：半导体存储器件包括经由晶体管连接到存储单元的第一位线，传输门，经由传输门连接到第一位线的第二位线，连接到第二位线的读出放大器，第一预充电用于对第一位线进行预充电的电路，用于对第二位线进行预充电的第二预充电电路，在关闭传输门之后由第一预充电电路对第一位线进行预充电的控制电路，随后通过第二位线预先充电第二位线第二预充电电路。

18. 发明授权

US08001450B2 Semiconductor memory device capable of changing ECC code length 有权
标题翻译：能够改变ECC码长度的半导体存储器件
公开(公告)号：US08001450B2
公开(公告)日：2011-08-16
申请号：US11878867
申请日：2007-07-27
申请人： Yasuhiro Onishi , Toshiya Miyo
发明人： Yasuhiro Onishi , Toshiya Miyo
IPC分类号： H03M13/00
CPC分类号： G06F11/1048
摘要： The data memory cell array and parity memory cell array in the memory cell array has a constitution that is capable of corresponding with a plurality of ECC code lengths. An input-side parity generation circuit that generates parities from write data, an output-side parity generation circuit that generates parities from read data, and a syndrome generation circuit that generates a syndrome bit that indicates an error bit from the read parity bits and generated parity bits are constituted so as to be capable of switching, according to the plurality of ECC code lengths.
摘要翻译：存储单元阵列中的数据存储单元阵列和奇偶校验存储单元阵列具有能够对应于多个ECC码长度的结构。从写入数据产生奇偶校验的输入侧奇偶校验生成电路，从读取数据生成奇偶校验的输出侧奇偶校验生成电路，以及从读出的奇偶校验位生成表示错误位的校正子位的校正子生成电路，奇偶校验位构成为能够根据多个ECC码长度进行切换。

19. 发明申请

US20080034270A1 Semiconductor memory device capable of changing ECC code length 有权
标题翻译：能够改变ECC码长度的半导体存储器件
公开(公告)号：US20080034270A1
公开(公告)日：2008-02-07
申请号：US11878867
申请日：2007-07-27
申请人： Yasuhiro Onishi , Toshiya Miyo
发明人： Yasuhiro Onishi , Toshiya Miyo
IPC分类号： G06F11/10
CPC分类号： G06F11/1048
摘要： The data memory cell array and parity memory cell array in the memory cell array has a constitution that is capable of corresponding with a plurality of ECC code lengths. An input-side parity generation circuit that generates parities from write data, an output-side parity generation circuit that generates parities from read data, and a syndrome generation circuit that generates a syndrome bit that indicates an error bit from the read parity bits and generated parity bits are constituted so as to be capable of switching, according to the plurality of ECC code lengths.
摘要翻译：存储单元阵列中的数据存储单元阵列和奇偶校验存储单元阵列具有能够对应于多个ECC码长度的结构。从写入数据产生奇偶校验的输入侧奇偶校验生成电路，从读取数据生成奇偶校验的输出侧奇偶校验生成电路，以及从读出的奇偶校验位生成表示错误位的校正子位的校正子生成电路，奇偶校验位构成为能够根据多个ECC码长度进行切换。

20. 发明授权

US08264869B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08264869B2
公开(公告)日：2012-09-11
申请号：US12779707
申请日：2010-05-13
申请人： Toshiya Miyo , Atsumasa Sako
发明人： Toshiya Miyo , Atsumasa Sako
IPC分类号： G11C11/24
CPC分类号： G11C5/145 , G11C8/18 , G11C11/4074
摘要： A semiconductor storage device includes a memory cell array in which a memory cell including an MOS capacitor is arranged; a power supply unit that supplies a plate voltage to a plate line that is coupled to a gate electrode of the MOS capacitor; and a switch that couples the plate line to a first power supply line when an access to the memory cell array is caused.
摘要翻译：一种半导体存储装置，包括配置有包括MOS电容器的存储单元的存储单元阵列; 电源单元，其将板电压提供给耦合到所述MOS电容器的栅电极的板线; 以及当引起对存储单元阵列的访问时将板线耦合到第一电源线的开关。

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