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11. 发明授权

US06320454B1 Low power voltage regulator circuit for use in an integrated circuit device 有权
标题翻译：用于集成电路器件的低功率稳压电路
公开(公告)号：US06320454B1
公开(公告)日：2001-11-20
申请号：US09586664
申请日：2000-06-01
申请人： Saroj Pathak , James E. Payne , Harry H. Kuo
发明人： Saroj Pathak , James E. Payne , Harry H. Kuo
IPC分类号： G05F110
CPC分类号： G05F1/465
摘要： A voltage regulator circuit that receives an input signal and provides an output signal that is clamped at a specified voltage desired for an internal circuit. The disclosed voltage regulator circuit includes a plurality of subcircuits including a voltage tracking subcircuit in which the output voltage tracks the input voltage with no voltage drop when the input voltage starts to rise from zero volts. If the input voltage increases to a desired voltage level for the internal circuit, the voltage tracking subcircuit clamps the output voltage to remain at that voltage. If the input voltage further increases to a higher voltage, the voltage tracking subcircuit is disabled and one of a plurality of voltage maintaining subcircuit takes control so that the output voltage remains at the desired voltage for the internal circuit.
摘要翻译：电压调节器电路，其接收输入信号并提供被钳位在内部电路所需的指定电压下的输出信号。所公开的电压调节器电路包括多个子电路，其包括电压跟踪子电路，其中当输入电压从零伏开始上升时，输出电压跟踪输入电压而没有电压降。如果输入电压增加到内部电路的所需电压电平，则电压跟踪分支电路将输出电压钳位以保持在该电压。如果输入电压进一步增加到较高的电压，则电压跟踪子电路被禁止，并且控制多个电压保持子电路中的一个，使得输出电压保持在内部电路的期望电压。

12. 发明授权

US6140993A Circuit for transferring high voltage video signal without signal loss 失效
标题翻译：用于传输高电压视频信号的电路，无信号丢失
公开(公告)号：US6140993A
公开(公告)日：2000-10-31
申请号：US97866
申请日：1998-06-16
申请人： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
发明人： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
IPC分类号： G09G3/20 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/3677 , G09G2300/0876 , G09G2310/0289 , G09G3/2011 , G09G3/2074
摘要： A circuit for transferring high voltage analog video signals while enabling the use of conventional low voltage logic levels includes a first transistor powered by a high voltage power source to bias a pass transistor at a high voltage level. The pass transistor receives a high voltage video signal and because of the high voltage bias is able to pass the video signal without attenuation of the signal due to feedthrough effects, thus preserving the fidelity of the video signal. A second transistor provides a ground potential which operates to turn OFF the pass transistor, thus disabling the transfer of the video signal therethrough. A third transistor operatively coupled to the first transistor operates to turn OFF the first transistor when the second transistor is in operation.
摘要翻译：用于传送高压模拟视频信号同时能够使用常规低电压逻辑电平的电路包括由高电压电源供电的第一晶体管，以在高电压电平下偏置传输晶体管。传输晶体管接收高电压视频信号，并且由于高电压偏压能够通过视频信号而不会由于馈通效应而导致信号衰减，从而保持视频信号的保真度。第二晶体管提供接地电位，其操作以关闭传输晶体管，从而禁止视频信号通过其传输。可操作地耦合到第一晶体管的第三晶体管操作以在第二晶体管工作时关断第一晶体管。

13. 发明授权

US6115305A Method and apparatus for testing a video display chip 有权
标题翻译：用于测试视频显示芯片的方法和装置
公开(公告)号：US6115305A
公开(公告)日：2000-09-05
申请号：US333805
申请日：1999-06-15
申请人： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
发明人： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
IPC分类号： G01R31/02 , G01R31/3185 , G09G3/20 , G11C29/02 , G11C29/10 , G11C29/34 , G11C7/00
CPC分类号： G11C29/02 , G01R31/31855
摘要： A video chip includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register. There is a circuit for the column lines and for the row lines. A bit pattern is driven onto the column or the row lines and received in the corresponding test circuitry. The pattern is read out and compared against the input pattern to detect faulty lines.
摘要翻译：视频芯片包括用于检测开路和短路的测试电路。该电路包括串联连接的晶体管链和测试寄存器。列线和行线都有一个电路。位模式被驱动到列或行线上并被接收在相应的测试电路中。该模式被读出并与输入模式进行比较以检测故障线路。

14. 发明授权

US5781469A Bitline load and precharge structure for an SRAM memory 失效
标题翻译： SRAM存储器的位线负载和预充电结构
公开(公告)号：US5781469A
公开(公告)日：1998-07-14
申请号：US788523
申请日：1997-01-24
申请人： Saroj Pathak , James E. Payne
发明人： Saroj Pathak , James E. Payne
IPC分类号： G11C11/41 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419
摘要： An SRAM configures its bitline load structure to implement one of three different precharge schemes, none of which use an ATD circuit. The SRAM monitors its WRITE/READ pin and initiates a first precharging scheme when the SRAM is in a read mode. In the first precharging scheme, every complementary bitline pair is directly coupled to Vcc via a first pmos transistor which is permanently turned on, regardless of whether a memory cell is being read or not. Additionally, both true and false bitlines in every complementary bitline pair are coupled together via a pmos transistor as long as the SRAM remains in a read mode. When in a write mode, the second precharging scheme is initiated causing the second pmos transistor to be turned off and only the first pmos transistors remain active. Thus, all complementary bitline pairs which are not selected for a write operation are pulled up to Vcc by the first pmos transistors. The termination of the write mode activates the third precharging scheme which causes all the bitlines, both true and false, within the memory array to be momentarily shorted together. The cumulative equivalent capacitance of the complementary bitlines pairs which were not selected for a write operation help to pull up the few complementary bitlines pairs which were pull down during the previous write operation.
摘要翻译： SRAM配置其位线负载结构以实现三种不同的预充电方案中的一种，其中一种不使用ATD电路。当SRAM处于读取模式时，SRAM监视其写入/读取引脚并启动第一个预充电方案。在第一预充电方案中，不管存储器单元是否被读取，每个互补位线对都经由永久地导通的第一个pmos晶体管直接耦合到Vcc。另外，只要SRAM保持在读取模式，每个互补位线对中的真位和错位都通过pmos晶体管耦合在一起。当处于写入模式时，启动第二预充电方案，使第二个pmos晶体管截止，并且只有第一个pmos晶体管保持有效。因此，未被选择用于写操作的所有互补位线对被第一pmos晶体管上拉至Vcc。写入模式的终止激活第三个预充电方案，这导致存储器阵列内的所有位线都为真和假，以便短暂地短路。补充位线对的累积等效电容未被选择用于写入操作有助于拉出在之前的写入操作期间被拉低的少数互补位线对。

15. 发明授权

US5731734A Zero power fuse circuit 失效
标题翻译：零电源保险丝电路
公开(公告)号：US5731734A
公开(公告)日：1998-03-24
申请号：US726956
申请日：1996-10-07
申请人： Jagdish Pathak , James E. Payne , Saroj Pathak
发明人： Jagdish Pathak , James E. Payne , Saroj Pathak
IPC分类号： H01L21/8238 , G11C29/04 , H01L21/82 , H01L27/092 , H03K3/356 , H03K17/687
CPC分类号： H03K3/356008 , H03K3/356182
摘要： A zero power fuse circuit includes a latch means having two inputs, a first input being latched to ground and a second input being latched to V.sub.cc. The latch means is triggered either by a momentary contact of the first input to ground or by the momentary contact of the second input to V.sub.cc. A first embodiment includes two fuse element/capacitor pairs each coupled to one of the two inputs of the latch means. A second embodiment includes a pull-up transistor and a fuse element/capacitor pair, coupled to the first and second inputs respectively. A third embodiment includes a pull-down transistor and a fuse element/capacitor pair respectively coupled to the second and first inputs of the latch means.
摘要翻译：零功率熔断器电路包括具有两个输入的锁存装置，第一输入端被锁存到地，第二输入端被锁存到Vcc。闩锁装置通过第一输入端与地之间的瞬时接触或第二输入端瞬间接触到Vcc来触发。第一实施例包括每个耦合到锁存装置的两个输入之一的两个熔丝元件/电容器对。第二实施例包括分别耦合到第一和第二输入的上拉晶体管和熔丝元件/电容器对。第三实施例包括分别耦合到锁存装置的第二和第一输入端的下拉晶体管和熔丝元件/电容器对。

16. 发明授权

US5680346A High-speed, non-volatile electrically programmable and erasable cell and method 失效
标题翻译：高速，非易失性电子可编程和可擦除电池及方法
公开(公告)号：US5680346A
公开(公告)日：1997-10-21
申请号：US672299
申请日：1996-06-28
申请人： Saroj Pathak , James E. Payne
发明人： Saroj Pathak , James E. Payne
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/0433 , H01L27/115
摘要： A non-volatile programmable circuit having programming and read bitlines, a non-volatile memory cell, and a read select transistor, and a method for its operation. The non-volatile memory cell is programmable through the programming bitline. The read select transistor is connected between the non-volatile memory cell and the read bitline. During read operation, the programming bitline is grounded and programmed information is readable onto the read bitline. During programming operation, the read bitline is grounded, and programmed information is programmable into the non-volatile memory cell for storage and retention.
摘要翻译：具有编程和读取位线的非易失性可编程电路，非易失性存储单元和读选择晶体管及其操作方法。非易失性存储单元可通过编程位线进行编程。读选择晶体管连接在非易失性存储单元和读位线之间。在读操作期间，编程位线接地，编程信息可读取到读位线上。在编程操作期间，读取位线接地，编程信息可编程到非易失性存储单元中以进行存储和保留。

17. 发明授权

US5473500A Electrostatic discharge circuit for high speed, high voltage circuitry 失效
标题翻译：用于高速，高压电路的静电放电电路
公开(公告)号：US5473500A
公开(公告)日：1995-12-05
申请号：US180673
申请日：1994-01-13
申请人： James E. Payne , Saroj Pathak , Glen A. Rosendale
发明人： James E. Payne , Saroj Pathak , Glen A. Rosendale
IPC分类号： H01L27/088 , H01L21/8234 , H02H7/20 , H02H9/04 , H03K19/003 , H04B15/00 , H02H3/22
CPC分类号： H03K19/00315 , H02H9/046
摘要： A protection circuit includes a first controlled path for discharging negative ESD pulses introduced at a signal node. The first controlled path is from the signal node to V.sub.cc via the source and drain electrodes of a first transistor. The gate of the transistor is at a soft ground by connection of the gate through a resistor and an inverter to a fixed voltage supply potential (V.sub.cc). A second controlled path discharges positive ESD pulses via source and drain regions of serially connected second and third transistors to ground. The second transistor has a gate tied at V.sub.cc by means of a resistor and inverter to ground. The third transistor is at soft ground by means of a resistor and inverter to V.sub.cc. The third transistor is turned on by a positive voltage exceeding the threshold voltage of the third transistor, but the second transistor prevents damage to the third transistor by limiting the voltage applied to the third transistor. The protection circuit may include a third controlled path through a fourth transistor, if low voltage circuitry is tied to the signal node. The fourth transistor includes a gate that is tied high by connection of the gate to ground via a transistor and inverter.
摘要翻译：保护电路包括用于放大在信号节点处引入的负ESD脉冲的第一控制路径。第一受控路径经由第一晶体管的源极和漏极从信号节点到Vcc。晶体管的栅极通过栅极通过电阻和逆变器连接到固定电压电位（Vcc）而处于软接地。第二控制路径通过串联的第二和第三晶体管的源极和漏极区域将正的ESD脉冲放电到地。第二晶体管具有通过电阻器和反相器接地的Vcc连接的栅极。第三个晶体管通过电阻器和逆变器在Vcc处于软接地。第三晶体管被超过第三晶体管的阈值电压的正电压导通，但是第二晶体管通过限制施加到第三晶体管的电压来防止对第三晶体管的损坏。如果低电压电路连接到信号节点，则保护电路可以包括通过第四晶体管的第三受控路径。第四晶体管包括通过晶体管和反相器将栅极连接到地而被连接的栅极。

18. 发明授权

US5383193A Method for testing non-volatile memories 失效
标题翻译：测试非易失性存储器的方法
公开(公告)号：US5383193A
公开(公告)日：1995-01-17
申请号：US951207
申请日：1992-09-25
申请人： Saroj Pathak , Glen A. Rosendale , James E. Payne
发明人： Saroj Pathak , Glen A. Rosendale , James E. Payne
IPC分类号： G11C29/44 , G11C29/52 , G11C29/00
CPC分类号： G11C29/52 , G11C29/44
摘要： A method is provided for testing a non-programmable non-volatile memory which does not require the writing or erasing of any cells and permits the testing of all normal memory cells. Testing occurs from the device I/O pins and is useful in cases where EPROM memory cells have been bulk erased and placed within an ultraviolet-opaque package. The non-volatile memory is of the type having memory banks of rows and columns. Each bank must have address decoders and means for changing addresses between banks. A separate auxiliary cell or row of cells in a state different from the non-programmed state is provided. An address is supplied for the auxiliary cells and then for the normal cells and the interval between addressing the normal cells and the appearance of an output signal is measured and compared with a predetermined fixed limit. If the limit is exceeded, the address is identified as that of a weak cell whose speed does not meet product specifications. In suitably equipped memories, the addresses of weak cells can be recorded and redundant cell groups substituted as replacements.
摘要翻译：提供了一种用于测试不需要写入或擦除任何单元并且允许测试所有正常存储器单元的非可编程非易失性存储器的方法。测试发生在器件I / O引脚上，并且在EPROM存储器单元已被批量擦除并放置在不透紫外线的封装内的情况下很有用。非易失性存储器是具有行和列的存储体的类型。每个银行必须具有地址解码器和用于更改银行之间的地址的手段。提供了与非编程状态不同的单独的辅助单元或单元行。为辅助单元提供地址，然后为正常单元提供地址，并测量寻址正常单元之间的间隔和输出信号的出现，并将其与预定的固定限制进行比较。如果超出限制，则该地址被识别为速度不符合产品规格的弱电池的地址。在适当配置的存储器中，可以记录弱电池的地址，并将冗余的电池组替换为替换。

19. 发明授权

US08560386B2 Online map advertising 有权
标题翻译：在线地图广告
公开(公告)号：US08560386B2
公开(公告)日：2013-10-15
申请号：US13486160
申请日：2012-06-01
申请人： Brandon Badger , James E. Payne , Michael S. Perrow
发明人： Brandon Badger , James E. Payne , Michael S. Perrow
IPC分类号： G06Q40/00
CPC分类号： G06Q30/0275 , G06Q30/02 , G06Q30/0251 , G06Q30/08 , G06Q40/04 , H04W4/02 , H04W4/21
摘要： Systems and methods for selecting advertisements for presentation in a map space are disclosed. Map requests are received, map spaces identified, advertisement bids are received for advertisement space within the map spaces, and advertisements are selected for presentation in the map space based on the advertisement bids. The advertisement bids can be selected through an auction.
摘要翻译：公开了用于选择在地图空间中呈现的广告的系统和方法。收到地图请求，识别地图空间，收到地图空间内广告空间的广告投标，并根据广告投标选择广告进行地图空间呈现。可以通过拍卖来选择广告投标。

20. 发明授权

US06744291B2 Power-on reset circuit 有权
公开(公告)号：US06744291B2
公开(公告)日：2004-06-01
申请号：US10232636
申请日：2002-08-30
申请人： James E. Payne , Harry H. Kuo , Neville B. Ichhaporia , Jami N. Wang
发明人： James E. Payne , Harry H. Kuo , Neville B. Ichhaporia , Jami N. Wang
IPC分类号： H03L700
CPC分类号： H03K17/145 , H03K17/223 , H03K2217/0036
摘要： A power-on reset (POR) circuit comprises a transistor connected ad diodes for setting temperature time delay coupled to a power supply voltage, a transistor switch, and buffering circuits. The trip point voltage of the POR circuit depends only on one type of transistor, such as the switching transistor so that the p-to-n skew variations do not affect the trip point. The switching transistor has a resistor connected from base to ground and another resistor connected to the power supply voltage to limit current flow during transitions.

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