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11. 发明授权

US06826090B1 Apparatus and method for a radiation resistant latch 失效
标题翻译：用于防辐射闩锁的装置和方法
公开(公告)号：US06826090B1
公开(公告)日：2004-11-30
申请号：US10455161
申请日：2003-06-05
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： G11C700
CPC分类号： G11C7/02 , G11C7/24
摘要： In one form of the invention, a radiation resistant latch has an overall output node, and first, second and third sublatches. The sublatches each have input circuitry, an output node coupled to the sublatch's input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and responsively generate binary-state output signals on their respective output nodes. The first and second sublatches are coupled to the third sublatch and the third sublatch has its output signal coupled to the overall output node such that if any one of the three sublatches is subjected to a radiation induced erroneous change of state, the output signals of the other two sublatches reduce an effect of the third sublatch feedback circuitry on an overall output signal for the latch.
摘要翻译：在本发明的一种形式中，耐辐射闩锁具有总输出节点以及第一，第二和第三子实体。这些分样具有输入电路，耦合到分页输入电路的输出节点和耦合到分页输出节点的反馈电路，用于加强子画面的输出信号。这些副作用可操作以在它们各自的输入电路处接收数据信号，并在其各自的输出节点上响应地产生二进制状态输出信号。第一和第二子集合被耦合到第三子交集，并且第三子选项具有耦合到整个输出节点的输出信号，使得如果三个子集合中的任何一个受到辐射引起的状态的错误改变，则输出信号其他两个分样可以减少第三个分支反馈电路对锁存器的总输出信号的影响。

12. 发明授权

US6046606A Soft error protected dynamic circuit 失效
标题翻译：软错误保护动态电路
公开(公告)号：US6046606A
公开(公告)日：2000-04-04
申请号：US10200
申请日：1998-01-21
申请人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
发明人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
IPC分类号： H03K19/003 , G06F11/00 , H03K19/096 , H03K19/094 , H03K19/20
CPC分类号： G06F11/00 , G06F11/004
摘要： A method and apparatus is effective to preserve logic state potential levels in logic circuitry notwithstanding alpha particle collisions. Cross-coupled circuitry, including active devices, are implemented in a complementary logic circuit arrangement to hold current logic values in the event of a premature switching such as a switching that may be induced by alpha particle collision with the semiconductor logic circuit. Stabilizing transistor switching devices are arranged to sense an inappropriate or premature switching initiation and respond thereto by operating to maintain the appropriate logic levels within the logic circuitry. In one embodiment, the internal node of an upper circuit in a dual-rail logic circuit is connected to a gate terminal of a cross-coupled PFET device in the lower circuit. The cross-coupled PFET device is operable to sense an initiated untimely switching action in the upper circuit and effect a re-application of the holding PFET in the upper circuit to re-establish the appropriate logic potential levels in the upper circuit.
摘要翻译：尽管存在α粒子碰撞，但是方法和装置有效地保持逻辑电路中的逻辑状态电位电平。包括有源器件的交叉耦合电路在互补逻辑电路装置中实现，以在诸如可能由半导体逻辑电路的α粒子碰撞引起的切换的过早切换的情况下保持当前逻辑值。稳定晶体管开关器件被布置为感测不适当或过早的开关启动，并通过操作来响应于其来维持逻辑电路内的适当的逻辑电平。在一个实施例中，双轨逻辑电路中的上电路的内部节点连接到下电路中的交叉耦合PFET器件的栅极端子。交叉耦合PFET器件可操作以感测上电路中引发的不合时宜的开关动作，并且实现上电路中保持PFET的重新施加，以重新建立上电路中适当的逻辑电位电平。

13. 发明授权

US6052008A Generation of true and complement signals in dynamic circuits 失效
标题翻译：在动态电路中产生真实和补码信号
公开(公告)号：US6052008A
公开(公告)日：2000-04-18
申请号：US892861
申请日：1997-07-14
申请人： Sam Gat-Shang Chu , Visweswaya Rao Kodali , Michael Ju Hyeok Lee
发明人： Sam Gat-Shang Chu , Visweswaya Rao Kodali , Michael Ju Hyeok Lee
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A logic circuit includes an inverter for generating a complement of an output signal from another logic circuit for input to a dynamic logic circuit. The dynamic logic circuit is capable of receiving both the complement signal and dynamic input signals during both the precharge and evaluate phases of the dynamic logic circuit. The complement signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages with the dynamic logic circuit still capable of correctly evaluating the implemented logical operation of the dynamic logic circuit on the complement signal and the dynamic input signals. A p-channel FET is coupled between the internal precharge node and a voltage reference source where the gate electrode of the p-channel FET device receives the complement signal. Such a configuration eliminates the need for duplicate circuitry necessary to generate the complement signal for use by the dynamic logic circuit and also eliminates the addition of clock skew necessary to prevent potential false switching when using a complement signal generated by simple inversion.
摘要翻译：逻辑电路包括用于产生来自另一逻辑电路的输出信号的补码以输入到动态逻辑电路的反相器。在动态逻辑电路的预充电和评估阶段期间，动态逻辑电路能够接收补码信号和动态输入信号。允许补码信号在这样的阶段期间从低电平切换到高电平和高电平，而动态逻辑电路仍然能够正确地评估动态逻辑电路在补码信号上的逻辑运算和动态输入信号。 p沟道FET耦合在内部预充电节点和p型沟道FET器件的栅电极接收补码信号的电压参考源之间。这种配置消除了生成用于由动态逻辑电路使用的补码信号所需的重复电路的需要，并且还消除了当使用由简单反演产生的补码信号时防止潜在的错开关所必需的时钟偏移的相加。

14. 发明授权

US5852373A Static-dynamic logic circuit 失效
标题翻译：静态动态逻辑电路
公开(公告)号：US5852373A
公开(公告)日：1998-12-22
申请号：US723814
申请日：1996-09-30
申请人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
发明人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
IPC分类号： H03K19/0175 , H03K19/096 , H03K19/0948
CPC分类号： H03K19/0963
摘要： A dynamic logic circuit is capable of receiving both dynamic and static input signals during both the precharge and evaluate phases of the logic circuit, and the static input signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages and the logic circuit is still capable of correctly evaluating the implemented logical operation on the static and dynamic input signals. This is performed in CMOS by coupling a PFET between the internal precharge node and a voltage reference source where the gate electrode of the PFET device receives the static input signal.
摘要翻译：动态逻辑电路能够在逻辑电路的预充电和评估阶段期间接收动态和静态输入信号，并且静态输入信号被允许从低电平切换到高电平和高电平在这种阶段期间的低电平，并且逻辑电路仍然能够正确评估对静态和动态输入信号的实现的逻辑运算。这通过在内部预充电节点和PFET器件的栅电极接收静态输入信号的电压参考源之间耦合PFET来实现。

15. 发明授权

US06002271A Dynamic MOS logic circuit without charge sharing noise 失效
标题翻译：动态MOS逻辑电路，无电荷共享噪声
公开(公告)号：US06002271A
公开(公告)日：1999-12-14
申请号：US854368
申请日：1997-05-12
申请人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
发明人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： Circuitry for eliminating charge sharing noise in MOS dynamic logic circuits is described. Dynamic logic circuits having stacks of MOS devices controlling the state of a common node defining the output logic state of the circuit are susceptible to charge sharing noise. This noise ultimately arises from leakage and stray capacitances at the nodes between MOS devices in each stack which the common node must supply. The noise is eliminated by employing MOS devices associated with the MOS devices in the stacks to couple the nodes between stack MOS devices to a supply voltage until their associated stack device changes logic state. On the changing state of the associated stack device, the node charging MOS device turns off, allowing the nodes to assume states defined by the input signals to the dynamic logic circuit.
摘要翻译：描述用于消除MOS动态逻辑电路中的电荷共享噪声的电路。具有控制限定电路的输出逻辑状态的公共节点的状态的MOS器件堆叠的动态逻辑电路容易受到电荷共享噪声的影响。这种噪声最终来自公共节点必须提供的每个堆叠中的MOS器件之间的节点处的泄漏和杂散电容。通过使用与堆叠中的MOS器件相关联的MOS器件来消除噪声，以将堆叠MOS器件之间的节点耦合到电源电压，直到其相关联的堆栈器件改变逻辑状态。在相关联的堆叠设备的变化状态下，节点充电MOS器件关闭，允许节点采取由输入信号定义到动态逻辑电路的状态。

16. 发明授权

US06341095B1 Apparatus for increasing pulldown rate of a bitline in a memory device during a read operation 有权
标题翻译：一种用于在读取操作期间增加存储器件中位线的下拉速率的装置
公开(公告)号：US06341095B1
公开(公告)日：2002-01-22
申请号：US09788819
申请日：2001-02-21
申请人： Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： G11C1300
CPC分类号： G11C11/419 , G11C7/12
摘要： An apparatus for increasing pulldown rate of a bitline in a memory device during a read operation is disclosed. The memory device includes a pair of complementary differential bitlines, and each of the complementary differential bitlines has a precharge transistor. The memory device also includes multiple storage cells coupled between the complementary differential bitlines. Furthermore, each of the complementary differential bitlines has a discharge transistor for increasing the pulldown rate of a respective bitline during a read operation.
摘要翻译：公开了一种用于在读取操作期间增加存储器件中的位线的下拉速率的装置。存储器件包括一对互补差分位线，并且每个互补差分位线具有预充电晶体管。存储器件还包括耦合在互补差分位线之间的多个存储单元。此外，每个互补差分位线具有用于在读取操作期间增加相应位线的下拉速率的放电晶体管。

17. 发明授权

US07116569B2 Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare mask 失效
标题翻译：通过使用比较掩码来选择内容可寻址存储器的操作特性的方法和装置
公开(公告)号：US07116569B2
公开(公告)日：2006-10-03
申请号：US11055803
申请日：2005-02-11
申请人： Joaquin Hinojosa , Eric Jason Fluhr , Michael Ju Hyeok Lee , Jose Angel Paredes , Ed Seewann
发明人： Joaquin Hinojosa , Eric Jason Fluhr , Michael Ju Hyeok Lee , Jose Angel Paredes , Ed Seewann
IPC分类号： G11C15/00
CPC分类号： G06F12/1027 , G06F2212/652 , G11C15/00
摘要： A CAM system is disclosed in which requests for address translation are provided as input search data to a dynamic compare bitline generator. The dynamic compare bitline generator also receives a compare mask and applies the compare mask to associated input search data bits on a per bit basis. The mask contains information that specifies a selected page size and a selected logic mode that can be applied to a compare array in which the specified search is conducted. The compare array is coupled to a data array to which the compare array indicates a result of the search.
摘要翻译：公开了一种CAM系统，其中将地址转换请求作为输入搜索数据提供给动态比较位线发生器。动态比较位线发生器还接收比较掩码，并以比特的形式将比较掩码应用于相关的输入搜索数据位。掩码包含指定所选页面大小的信息和可应用于进行指定搜索的比较数组的选定逻辑模式。比较数组耦合到比较数组指示搜索结果的数据阵列。

18. 发明授权

US07813189B2 Array data input latch and data clocking scheme 失效
标题翻译：阵列数据输入锁存器和数据时钟方案
公开(公告)号：US07813189B2
公开(公告)日：2010-10-12
申请号：US12166421
申请日：2008-07-02
申请人： Yuen Hung Chan , Elspeth Anne Huston , Michael Ju Hyeok Lee
发明人： Yuen Hung Chan , Elspeth Anne Huston , Michael Ju Hyeok Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22
摘要： A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues.
摘要翻译：一种用于高性能SRAM的数据输入锁存和时钟方法和装置，其中L1数据输入锁存器由正常本地时钟缓冲时钟信号和本地阵列时钟缓冲时钟信号的逻辑组合控制。时钟信号的这种逻辑组合使得L1锁存器的保持时间最小化提供了快速周期时间，其中SRAM宏可以处理连续写指令，同时避免早期模式问题。

19. 发明授权

US6107852A Method and device for the reduction of latch insertion delay 失效
标题翻译：用于减少锁存器插入延迟的方法和装置
公开(公告)号：US6107852A
公开(公告)日：2000-08-22
申请号：US81001
申请日：1998-05-19
申请人： Christopher McCall Durham , Michael Ju Hyeok Lee , Visweswara Rao Kodali , Harsh Dev Sharma
发明人： Christopher McCall Durham , Michael Ju Hyeok Lee , Visweswara Rao Kodali , Harsh Dev Sharma
IPC分类号： H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , H03K3/356156
摘要： A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main latch circuit, a feedback latch circuit and an output terminal. The main latch circuit is capable of receiving an input data signal and an input clock signal. The main latch circuit generates a latch output signal in response to the input data and clock signals. The feedback latch circuit is capable of receiving the latch output signal from the main latch circuit and storing the latch output signal. The feedback latch circuit is capable of generating a feedback latch circuit output signal which is received by the main latch circuit to maintain the latch output signal. The output terminal of the device is coupled to the feedback latch circuit for outputting a device output signal which is equal to the feedback latch circuit output signal.
摘要翻译：公开了一种用于减少与用于在数据处理系统中实现集成电路的电路中插入锁存相关联的惩罚的方法和装置。公开了一种半导体器件，其包括主锁存电路，反馈锁存电路和输出端子。主锁存电路能够接收输入数据信号和输入时钟信号。主锁存电路根据输入数据和时钟信号产生锁存输出信号。反馈锁存电路能够接收来自主锁存电路的锁存输出信号并存储锁存器输出信号。反馈锁存电路能够产生由主锁存电路接收的反馈锁存电路输出信号，以维持锁存输出信号。设备的输出端耦合到反馈锁存电路，用于输出等于反馈锁存电路输出信号的器件输出信号。

20. 发明授权

US07804728B2 Information handling system with SRAM precharge power conservation 失效
标题翻译：具有SRAM预充电功能的信息处理系统
公开(公告)号：US07804728B2
公开(公告)日：2010-09-28
申请号：US12185234
申请日：2008-08-04
申请人： Michael Ju Hyeok Lee , Bao G Truong
发明人： Michael Ju Hyeok Lee , Bao G Truong
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C11/413
摘要： An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation.
摘要翻译：信息处理系统（IHS）包括具有片上或片外SRAM阵列的处理器。在读取操作之后，控制电路可以指示SRAM阵列进行预充电操作，或者替代地指示SRAM阵列进行均衡的位线电压操作。读取操作可以遵循预充电操作或均衡位线电压操作。如果位线对的均衡电压显示出更多的预定量的电压，则控制电路可以指示SRAM阵列进行均衡的位线电压操作。否则，控制电路指示SRAM阵列在下一次读取操作之前进行预充电操作。

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