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1. 发明授权

US6052008A Generation of true and complement signals in dynamic circuits 失效
标题翻译：在动态电路中产生真实和补码信号
公开(公告)号：US6052008A
公开(公告)日：2000-04-18
申请号：US892861
申请日：1997-07-14
申请人： Sam Gat-Shang Chu , Visweswaya Rao Kodali , Michael Ju Hyeok Lee
发明人： Sam Gat-Shang Chu , Visweswaya Rao Kodali , Michael Ju Hyeok Lee
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A logic circuit includes an inverter for generating a complement of an output signal from another logic circuit for input to a dynamic logic circuit. The dynamic logic circuit is capable of receiving both the complement signal and dynamic input signals during both the precharge and evaluate phases of the dynamic logic circuit. The complement signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages with the dynamic logic circuit still capable of correctly evaluating the implemented logical operation of the dynamic logic circuit on the complement signal and the dynamic input signals. A p-channel FET is coupled between the internal precharge node and a voltage reference source where the gate electrode of the p-channel FET device receives the complement signal. Such a configuration eliminates the need for duplicate circuitry necessary to generate the complement signal for use by the dynamic logic circuit and also eliminates the addition of clock skew necessary to prevent potential false switching when using a complement signal generated by simple inversion.
摘要翻译：逻辑电路包括用于产生来自另一逻辑电路的输出信号的补码以输入到动态逻辑电路的反相器。在动态逻辑电路的预充电和评估阶段期间，动态逻辑电路能够接收补码信号和动态输入信号。允许补码信号在这样的阶段期间从低电平切换到高电平和高电平，而动态逻辑电路仍然能够正确地评估动态逻辑电路在补码信号上的逻辑运算和动态输入信号。 p沟道FET耦合在内部预充电节点和p型沟道FET器件的栅电极接收补码信号的电压参考源之间。这种配置消除了生成用于由动态逻辑电路使用的补码信号所需的重复电路的需要，并且还消除了当使用由简单反演产生的补码信号时防止潜在的错开关所必需的时钟偏移的相加。

2. 发明授权

US07015723B2 Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation 失效
标题翻译：动态静态逻辑控制元件，用于发出控制信号结束与逻辑评估之间的间隔
公开(公告)号：US07015723B2
公开(公告)日：2006-03-21
申请号：US10922271
申请日：2004-08-19
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： H03K19/00
CPC分类号： H03K19/0963
摘要： A dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation provides a compact circuit for blocking the indication of a non-evaluated state of a dynamic logic gate until a control signal has ended. The control signal is connected to a precharge input of the control element and a summing node is connected to one or more evaluation trees and to the control element output via an inverter. The inverter is connected to an override circuit that forces the output of the control element to a state opposite the precharge state until the control signal has ended. The output of the control element then assumes a state corresponding to the precharge state until an evaluation occurs. The control element output thus produces a window signal indicating the interval between the end of the control signal and the evaluation.
摘要翻译：用于发信号通知控制信号的结束与逻辑评估之间的间隔的动态静态逻辑控制元件提供紧凑的电路，用于阻止动态逻辑门的未评估状态的指示，直到控制信号结束为止。控制信号连接到控制元件的预充电输入，并且求和节点经由逆变器连接到一个或多个评估树和控制元件输出。逆变器连接到超控电路，其将控制元件的输出强制到与预充电状态相反的状态，直到控制信号结束。然后，控制元件的输出呈现与预充电状态相对应的状态，直到评估发生。因此，控制元件输出产生指示控制信号的结束与评估之间的间隔的窗口信号。

3. 发明授权

US07002860B2 Multilevel register-file bit-read method and apparatus 有权
标题翻译：多级寄存器 - 文件位读取方法和装置
公开(公告)号：US07002860B2
公开(公告)日：2006-02-21
申请号：US10703017
申请日：2003-11-06
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： G11C7/12 , G11C8/00 , G11C11/41
CPC分类号： G11C7/1012 , G11C7/1051 , G11C8/10
摘要： A bit-read apparatus includes a first decoder and N multiplexers, each having Q output nodes and Q pull-ups coupled thereto. Respective multiplexers have M selectors coupled to N×M respective select lines and register-file cells. The selectors are in Q groups coupled to respective output nodes. Each multiplexer has a logic gate with inputs coupled to respective multiplexer output nodes. A second decoder is coupled to an N+1th multiplexer having R output nodes and R pull-ups coupled thereto. The N+1th multiplexer also has N selectors, coupled to respective select lines of the second decoder and respective output logic gates of the N multiplexers. The N selectors are in R groups coupled to the R nodes. An output logic gate for N+1th multiplexer has R inputs coupled respectively to the R nodes. Each pull-up of the multiplexers drives its respective multiplexer output node responsive to an address-bit signal.
摘要翻译：位读取装置包括第一解码器和N个多路复用器，每个具有与其耦合的Q个输出节点和Q个上拉电路。各个复用器具有耦合到NxM个选择线和寄存器文件单元的M个选择器。选择器处于耦合到相应输出节点的Q组中。每个复用器具有逻辑门，其输入耦合到相应的多路复用器输出节点。第二解码器耦合到具有耦合到其上的R个输出节点和R个上拉的第N + 1个多路复用器。第N + 1个多路复用器还具有N个选择器，耦合到第二解码器的相应选择线和N个多路复用器的相应输出逻辑门。 N个选择器位于耦合到R个节点的R组中。用于N + 1个多路复用器的输出逻辑门分别具有分别耦合到R个节点的R个输入。多路复用器的每个上拉响应地址位信号驱动其相应的多路复用器输出节点。

4. 发明授权

US6046606A Soft error protected dynamic circuit 失效
标题翻译：软错误保护动态电路
公开(公告)号：US6046606A
公开(公告)日：2000-04-04
申请号：US10200
申请日：1998-01-21
申请人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
发明人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
IPC分类号： H03K19/003 , G06F11/00 , H03K19/096 , H03K19/094 , H03K19/20
CPC分类号： G06F11/00 , G06F11/004
摘要： A method and apparatus is effective to preserve logic state potential levels in logic circuitry notwithstanding alpha particle collisions. Cross-coupled circuitry, including active devices, are implemented in a complementary logic circuit arrangement to hold current logic values in the event of a premature switching such as a switching that may be induced by alpha particle collision with the semiconductor logic circuit. Stabilizing transistor switching devices are arranged to sense an inappropriate or premature switching initiation and respond thereto by operating to maintain the appropriate logic levels within the logic circuitry. In one embodiment, the internal node of an upper circuit in a dual-rail logic circuit is connected to a gate terminal of a cross-coupled PFET device in the lower circuit. The cross-coupled PFET device is operable to sense an initiated untimely switching action in the upper circuit and effect a re-application of the holding PFET in the upper circuit to re-establish the appropriate logic potential levels in the upper circuit.
摘要翻译：尽管存在α粒子碰撞，但是方法和装置有效地保持逻辑电路中的逻辑状态电位电平。包括有源器件的交叉耦合电路在互补逻辑电路装置中实现，以在诸如可能由半导体逻辑电路的α粒子碰撞引起的切换的过早切换的情况下保持当前逻辑值。稳定晶体管开关器件被布置为感测不适当或过早的开关启动，并通过操作来响应于其来维持逻辑电路内的适当的逻辑电平。在一个实施例中，双轨逻辑电路中的上电路的内部节点连接到下电路中的交叉耦合PFET器件的栅极端子。交叉耦合PFET器件可操作以感测上电路中引发的不合时宜的开关动作，并且实现上电路中保持PFET的重新施加，以重新建立上电路中适当的逻辑电位电平。

5. 发明申请

US20060049850A1 Leakage sensing and keeper circuit for proper operation of a dynamic circuit 失效
标题翻译：泄漏检测和保持电路用于动态电路的正常运行
公开(公告)号：US20060049850A1
公开(公告)日：2006-03-09
申请号：US10937703
申请日：2004-09-09
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A method and apparatus for ensuring proper operation of a dynamic circuit is provided. A dynamic circuit instance has a plurality of outputs connected to a respective one of a plurality of leakage detector circuits. An output of each leakage detector circuit is connected with a respective one of a plurality of keeper circuits that reside at the dynamic circuit. Each of the plurality of keeper circuits has a unique size ratio with respect to a logic element size of the dynamic circuit.
摘要翻译：提供一种用于确保动态电路的正确操作的方法和装置。动态电路实例具有连接到多个泄漏检测器电路中的相应一个的多个输出。每个泄漏检测器电路的输出与位于动态电路的多个保持器电路中的相应一个连接。多个保持器电路中的每一个相对于动态电路的逻辑元件尺寸具有独特的尺寸比。

6. 发明授权

US06825691B1 Apparatus and method for a radiation resistant latch with integrated scan 失效
标题翻译：具有集成扫描功能的防辐射锁存器的装置和方法
公开(公告)号：US06825691B1
公开(公告)日：2004-11-30
申请号：US10455163
申请日：2003-06-05
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： H03K19173
CPC分类号： G11C11/4125
摘要： According to one form, a latch has an output node and sublatches. The sublatches each have an output node coupled to input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and to generate output signals on their respective output nodes. At least one sublatch output node is coupled to the latch output node. The output nodes of other ones of the sublatches are connected in the latch such that if any one of the sublatches is subjected to a radiation induced erroneous change of state the output signals of the other sublatches reduce an effect of the change on the latch output signal. The latch also includes a number of scanning-mode control switches coupled to ones of the sublatches for scanning data in or out.
摘要翻译：根据一种形式，锁存器具有输出节点和副组。这些副组件各自具有耦合到输入电路的输出节点和耦合到重叠器输出节点的反馈电路，用于加强子锁的输出信号。这些集合可操作以在它们各自的输入电路处接收数据信号，并在它们各自的输出节点上产生输出信号。至少一个子批输出节点耦合到锁存器输出节点。其他的一些子实体的输出节点连接在锁存器中，使得如果任何一个子实体受到辐射引起的状态的错误改变，则其他子集合的输出信号会减小锁存器输出信号的变化的影响。锁存器还包括多个扫描模式控制开关，其耦合到用于扫描数据的一个或多个子集。

7. 发明授权

US5852373A Static-dynamic logic circuit 失效
标题翻译：静态动态逻辑电路
公开(公告)号：US5852373A
公开(公告)日：1998-12-22
申请号：US723814
申请日：1996-09-30
申请人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
发明人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
IPC分类号： H03K19/0175 , H03K19/096 , H03K19/0948
CPC分类号： H03K19/0963
摘要： A dynamic logic circuit is capable of receiving both dynamic and static input signals during both the precharge and evaluate phases of the logic circuit, and the static input signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages and the logic circuit is still capable of correctly evaluating the implemented logical operation on the static and dynamic input signals. This is performed in CMOS by coupling a PFET between the internal precharge node and a voltage reference source where the gate electrode of the PFET device receives the static input signal.
摘要翻译：动态逻辑电路能够在逻辑电路的预充电和评估阶段期间接收动态和静态输入信号，并且静态输入信号被允许从低电平切换到高电平和高电平在这种阶段期间的低电平，并且逻辑电路仍然能够正确评估对静态和动态输入信号的实现的逻辑运算。这通过在内部预充电节点和PFET器件的栅电极接收静态输入信号的电压参考源之间耦合PFET来实现。

8. 发明授权

US07506230B2 Transient noise detection scheme and apparatus 有权
标题翻译：瞬态噪声检测方案和装置
公开(公告)号：US07506230B2
公开(公告)日：2009-03-17
申请号：US11050351
申请日：2005-02-03
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： G01R31/28
CPC分类号： G06F11/24
摘要： A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches. The second pair of latches is parallel to the first pair of latches. Both pairs of latches capture the input. However, the second pair of latches captures the input later in time relative to the first pair of latches latch. The captured input is then transferred from the first latch in each pair of latches to the second latch in each pair of latches. A comparison is made of the input in the two second latches. If the input captured in the two second latches is not the same, then a message is sent to a recovery unit.
摘要翻译：一种用于检测非数据流电路中的软错误的方法，系统和装置。在优选实施例中，在锁存系统处接收输入。闩锁系统由两对闩锁组成。第二对闩锁平行于第一对闩锁。两对锁存器捕获输入。然而，第二对锁存器相对于第一对锁存器锁存器在时间上稍后捕获输入。捕获的输入然后从每对闩锁中的第一锁存器传送到每对锁存器中的第二锁存器。比较两个第二个锁存器中的输入。如果在两个第二锁存器中捕获的输入不相同，则将信息发送到恢复单元。

9. 发明授权

US07202704B2 Leakage sensing and keeper circuit for proper operation of a dynamic circuit 失效
标题翻译：泄漏检测和保持电路用于动态电路的正常运行
公开(公告)号：US07202704B2
公开(公告)日：2007-04-10
申请号：US10937703
申请日：2004-09-09
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： H03K19/096 , H03K19/00 , H03K19/20 , H03K19/094 , G01R31/02
CPC分类号： H03K19/0963
摘要： A method and apparatus for ensuring proper operation of a dynamic circuit is provided. A dynamic circuit instance has a plurality of outputs connected to a respective one of a plurality of leakage detector circuits. An output of each leakage detector circuit is connected with a respective one of a plurality of keeper circuits that reside at the dynamic circuit. Each of the plurality of keeper circuits has a unique size ratio with respect to a logic element size of the dynamic circuit.
摘要翻译：提供一种用于确保动态电路的正确操作的方法和装置。动态电路实例具有连接到多个泄漏检测器电路中的相应一个的多个输出。每个泄漏检测器电路的输出与位于动态电路的多个保持器电路中的相应一个连接。多个保持器电路中的每一个相对于动态电路的逻辑元件尺寸具有独特的尺寸比。

10. 发明授权

US06002271A Dynamic MOS logic circuit without charge sharing noise 失效
标题翻译：动态MOS逻辑电路，无电荷共享噪声
公开(公告)号：US06002271A
公开(公告)日：1999-12-14
申请号：US854368
申请日：1997-05-12
申请人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
发明人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： Circuitry for eliminating charge sharing noise in MOS dynamic logic circuits is described. Dynamic logic circuits having stacks of MOS devices controlling the state of a common node defining the output logic state of the circuit are susceptible to charge sharing noise. This noise ultimately arises from leakage and stray capacitances at the nodes between MOS devices in each stack which the common node must supply. The noise is eliminated by employing MOS devices associated with the MOS devices in the stacks to couple the nodes between stack MOS devices to a supply voltage until their associated stack device changes logic state. On the changing state of the associated stack device, the node charging MOS device turns off, allowing the nodes to assume states defined by the input signals to the dynamic logic circuit.
摘要翻译：描述用于消除MOS动态逻辑电路中的电荷共享噪声的电路。具有控制限定电路的输出逻辑状态的公共节点的状态的MOS器件堆叠的动态逻辑电路容易受到电荷共享噪声的影响。这种噪声最终来自公共节点必须提供的每个堆叠中的MOS器件之间的节点处的泄漏和杂散电容。通过使用与堆叠中的MOS器件相关联的MOS器件来消除噪声，以将堆叠MOS器件之间的节点耦合到电源电压，直到其相关联的堆栈器件改变逻辑状态。在相关联的堆叠设备的变化状态下，节点充电MOS器件关闭，允许节点采取由输入信号定义到动态逻辑电路的状态。

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