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1. 发明授权

US6052008A Generation of true and complement signals in dynamic circuits 失效
标题翻译：在动态电路中产生真实和补码信号
公开(公告)号：US6052008A
公开(公告)日：2000-04-18
申请号：US892861
申请日：1997-07-14
申请人： Sam Gat-Shang Chu , Visweswaya Rao Kodali , Michael Ju Hyeok Lee
发明人： Sam Gat-Shang Chu , Visweswaya Rao Kodali , Michael Ju Hyeok Lee
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A logic circuit includes an inverter for generating a complement of an output signal from another logic circuit for input to a dynamic logic circuit. The dynamic logic circuit is capable of receiving both the complement signal and dynamic input signals during both the precharge and evaluate phases of the dynamic logic circuit. The complement signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages with the dynamic logic circuit still capable of correctly evaluating the implemented logical operation of the dynamic logic circuit on the complement signal and the dynamic input signals. A p-channel FET is coupled between the internal precharge node and a voltage reference source where the gate electrode of the p-channel FET device receives the complement signal. Such a configuration eliminates the need for duplicate circuitry necessary to generate the complement signal for use by the dynamic logic circuit and also eliminates the addition of clock skew necessary to prevent potential false switching when using a complement signal generated by simple inversion.
摘要翻译：逻辑电路包括用于产生来自另一逻辑电路的输出信号的补码以输入到动态逻辑电路的反相器。在动态逻辑电路的预充电和评估阶段期间，动态逻辑电路能够接收补码信号和动态输入信号。允许补码信号在这样的阶段期间从低电平切换到高电平和高电平，而动态逻辑电路仍然能够正确地评估动态逻辑电路在补码信号上的逻辑运算和动态输入信号。 p沟道FET耦合在内部预充电节点和p型沟道FET器件的栅电极接收补码信号的电压参考源之间。这种配置消除了生成用于由动态逻辑电路使用的补码信号所需的重复电路的需要，并且还消除了当使用由简单反演产生的补码信号时防止潜在的错开关所必需的时钟偏移的相加。

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