专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08975141B2 Dual work function FinFET structures and methods for fabricating the same 有权
标题翻译：双功能功能FinFET结构及其制造方法
公开(公告)号：US08975141B2
公开(公告)日：2015-03-10
申请号：US13563202
申请日：2012-07-31
申请人： Andy C. Wei , Bin Yang , Francis M. Tambwe
发明人： Andy C. Wei , Bin Yang , Francis M. Tambwe
IPC分类号： H01L21/336
CPC分类号： H01L27/11 , H01L21/823821 , H01L29/7843
摘要： A method for fabricating a dual-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the FinFET structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer.
摘要翻译：一种用于制造双功函数FinFET结构的方法，包括在FinFET结构的多个沟槽中的层中沉积第一功函数材料，在第一功函数材料层上沉积低电阻材料层，以及蚀刻低电阻材料层和来自FinFET结构的一部分的第一功函数材料层。该方法还包括在该部分的多个沟槽中的层中沉积第二功函数材料，并在第二功函数材料层上沉积应力材料层。

12. 发明授权

US08557666B2 Methods for fabricating integrated circuits 有权
公开(公告)号：US08557666B2
公开(公告)日：2013-10-15
申请号：US13231750
申请日：2011-09-13
申请人： Andy C. Wei , Peter Baars , Erik P. Geiss
发明人： Andy C. Wei , Peter Baars , Erik P. Geiss
IPC分类号： H01L21/336
CPC分类号： H01L21/823418 , H01L21/76224 , H01L21/76897 , H01L21/823431 , H01L21/823821 , H01L29/41783 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

13. 发明申请

US20130065371A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS 有权
标题翻译：制作集成电路的方法
公开(公告)号：US20130065371A1
公开(公告)日：2013-03-14
申请号：US13231750
申请日：2011-09-13
申请人： Andy C. Wei , Peter Baars , Erik P. Geiss
发明人： Andy C. Wei , Peter Baars , Erik P. Geiss
IPC分类号： H01L21/336 , H01L21/762 , H01L21/20
CPC分类号： H01L21/823418 , H01L21/76224 , H01L21/76897 , H01L21/823431 , H01L21/823821 , H01L29/41783 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.
摘要翻译：提供了用于制造集成电路的方法。一种方法包括将多个沟槽蚀刻成硅衬底并用绝缘材料填充沟槽以描绘多个间隔开的硅片。外延生长一层未掺杂的硅以形成翅片的上部未掺杂区域。虚拟门结构形成为覆盖并横向于多个翅片，并且后填充材料填充在虚拟栅极结构之间。去除虚拟栅极结构以暴露一部分散热片，并且将高k电介质材料和确定栅极电极材料的功函数沉积在鳍片的该部分上。去除后填充材料以暴露第二部分，并且在第二部分上形成金属硅化物接触。然后，将导电触点形成到功函数确定材料和金属硅化物。

14. 发明授权

US07977180B2 Methods for fabricating stressed MOS devices 有权
标题翻译：制造应力MOS器件的方法
公开(公告)号：US07977180B2
公开(公告)日：2011-07-12
申请号：US12330296
申请日：2008-12-08
申请人： Andrew M. Waite , Andy C. Wei
发明人： Andrew M. Waite , Andy C. Wei
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses.
摘要翻译：提供制造应力MOS器件的方法。在一个实施例中，该方法包括提供具有P阱区域并沉积覆盖P阱区域的多晶硅栅电极层的硅衬底。将P型掺杂剂离子注入到多晶硅栅电极层中以形成P型注入区，并且在P阱区上形成第一多晶硅栅电极。使用第一多晶硅栅电极作为蚀刻掩模将凹陷蚀刻到P阱区中。通过将硅衬底暴露于四甲基氢氧化铵来进行蚀刻步骤。在凹部内形成拉伸应力诱发材料。

15. 发明授权

US07180136B2 Biased, triple-well fully depleted SOI structure 有权
公开(公告)号：US07180136B2
公开(公告)日：2007-02-20
申请号：US11111409
申请日：2005-04-21
申请人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
发明人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
IPC分类号： H01L27/01
CPC分类号： H01L29/78648 , H01L29/78603 , H01L29/78606 , H01L29/78609
摘要： In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the bulk substrate being doped with a first type of dopant material and a first well formed in the bulk substrate, the first well being doped with a second type of dopant material that is of a type opposite the first type of dopant material. The device further comprises a second well formed in the bulk substrate within the first well, the second well being doped with a dopant material that is the same type as the first type of dopant material, the transistor being formed in the active layer above the second well, an electrical contact for the first well and an electrical contact for said second well. In one illustrative embodiment, a method of forming a transistor above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the bulk substrate being doped with a first type of dopant material is disclosed. The method comprises performing a first ion implant process using a dopant material that is of a type opposite the first type of dopant material to form a first well region within the bulk substrate, performing a second ion implant process using a dopant material that is the same type as the first type of dopant material to form a second well region in the bulk substrate within the first well, the transistor being formed in the active layer above the second well, forming a conductive contact to the first well and forming a conductive contact to the second well. The method further comprises a contact well formed in the bulk substrate within the first well, the contact well being comprised of a dopant material that is of the same type as the second type of dopant material, the contact well within the first well having a dopant concentration that is greater than a dopant concentration of the first well.

16. 发明授权

US06780686B2 Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions 有权
标题翻译：用于完全耗尽的SOI结构的掺杂方法，以及包含所得掺杂区的器件
公开(公告)号：US06780686B2
公开(公告)日：2004-08-24
申请号：US10104319
申请日：2002-03-21
申请人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
发明人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
IPC分类号： H01L21339
CPC分类号： H01L29/66772 , H01L29/78609 , H01L2924/0002 , H01L2924/00
摘要： The present invention is generally directed to doping methods for fully-depleted SOI structures, and a device comprising such resulting doped regions. In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the transistor being comprised of a gate electrode, the bulk substrate being doped with a dopant material at a first concentration level. The device further comprises a first doped region formed in the bulk substrate, the first doped region being doped with a dopant material that is the same type as the bulk substrate dopant material, wherein the concentration level of dopant material in the first doped region is greater than the first dopant concentration level in the bulk substrate, the first doped region being substantially aligned with the gate electrode.
摘要翻译：本发明一般涉及用于完全耗尽的SOI结构的掺杂方法，以及包括这样得到的掺杂区的器件。在一个说明性实施例中，该器件包括形成在绝缘体上硅衬底上的晶体管，该晶体管由体衬底，掩埋氧化物层和有源层组成，该晶体管由栅电极组成，该体衬底掺杂有掺杂剂材料在第一浓度水平。该器件还包括形成在本体衬底中的第一掺杂区域，该第一掺杂区域掺杂与本体衬底掺杂剂材料相同类型的掺杂剂材料，其中第一掺杂区域中掺杂剂材料的浓度水平较大比第一掺杂浓度水平高的第一掺杂浓度水平，第一掺杂区域基本上与栅电极对准。

17. 发明申请

US20130217221A1 DRY ETCH POLYSILICON REMOVAL FOR REPLACEMENT GATES 有权
标题翻译：用于替换盖的干燥多晶硅去除
公开(公告)号：US20130217221A1
公开(公告)日：2013-08-22
申请号：US13398991
申请日：2012-02-17
申请人： Chris M. PRINDLE , Klaus Hempel , Andy C. Wei
发明人： Chris M. PRINDLE , Klaus Hempel , Andy C. Wei
IPC分类号： H01L21/28
CPC分类号： H01L21/28114 , H01L21/32131 , H01L21/32134 , H01L21/32135 , H01L29/42376 , H01L29/51 , H01L29/66545
摘要： Semiconductor devices are formed with a gate last, high-K/metal gate process with complete removal of the polysilicon dummy gate and with a gap having a low aspect ratio for the metal fill. Embodiments include forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap, forming spacers adjacent opposite sides of the dummy gate electrode forming a gate trench therebetween, dry etching the nitride cap, tapering the gate trench top corners; performing a selective dry etch on a portion of the dummy gate electrode, and wet etching the remainder of the dummy gate electrode.
摘要翻译：半导体器件形成有最后的高K /金属栅极工艺，完全去除多晶硅虚拟栅极并且具有用于金属填充物的低纵横比的间隙。实施例包括在基板上形成虚拟栅电极，虚拟栅电极具有氮化物盖，在虚拟栅电极的相对侧上形成隔板，在其间形成栅极沟槽，干蚀刻氮化物盖，使栅极沟槽顶角逐渐变细; 在虚拟栅电极的一部分上进行选择性干蚀刻，并湿法蚀刻伪栅电极的其余部分。

18. 发明授权

US06876037B2 Fully-depleted SOI device 有权
标题翻译：全耗尽的SOI器件
公开(公告)号：US06876037B2
公开(公告)日：2005-04-05
申请号：US10796731
申请日：2004-03-09
申请人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
发明人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
IPC分类号： H01L27/12 , H01L21/336 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L29/78609 , H01L2924/0002 , H01L2924/00
摘要： The present invention is generally directed to a fully-depleted SOI device structure. In one illustrative embodiment, the device comprises first, second and third doped regions formed in the bulk substrate, wherein the dopant concentration level in the doped regions is greater than the dopant concentration in the bulk substrate. The first doped region is substantially aligned with the gate electrode of the device, while the second and third doped regions are vertically spaced apart from the first doped region.
摘要翻译：本发明一般涉及一种完全耗尽的SOI器件结构。在一个说明性实施例中，该器件包括形成在本体衬底中的第一，第二和第三掺杂区域，其中掺杂区域中的掺杂剂浓度水平大于本体衬底中的掺杂剂浓度。第一掺杂区域基本上与器件的栅电极对准，而第二和第三掺杂区域与第一掺杂区域垂直间隔开。

19. 发明授权

US06583016B1 Doped spacer liner for improved transistor performance 有权
标题翻译：掺杂间隔衬垫，用于改善晶体管性能
公开(公告)号：US06583016B1
公开(公告)日：2003-06-24
申请号：US10105522
申请日：2002-03-26
申请人： Andy C. Wei , Mark B. Fuselier , Ping-Chin Yeh
发明人： Andy C. Wei , Mark B. Fuselier , Ping-Chin Yeh
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/265 , H01L21/2652 , H01L29/6656 , H01L29/6659 , H01L29/66659 , H01L29/78603 , H01L29/78624
摘要： Semiconductor devices with improved transistor performance are fabricated by ion-implanting a dopant into the oxide liner to prevent or substantially reduce dopant out-diffusion from the shallow source/drain extensions. Embodiments include ion implanting a P-type dopant, such as B or BF2, using the gate electrode as a mask, to form shallow source/drain extensions, depositing a conformal oxide liner, and ion implanting the P-type impurity into the oxide liner at substantially the same dopant concentration as in the shallow source/drain extensions. Subsequent processing includes depositing a spacer layer, etching to form sidewall spacers, ion implanting to form deep moderate or heavy source/drain implants and activation annealing.
摘要翻译：具有改善的晶体管性能的半导体器件通过将掺杂剂离子注入到氧化物衬垫中来制造，以防止或基本上减少来自浅源极/漏极延伸部的掺杂剂扩散。实施例包括使用栅电极作为掩模离子注入诸如B或BF 2的P型掺杂剂，以形成浅源极/漏极延伸部，沉积共形氧化物衬垫，以及将P型杂质注入氧化物衬垫在与浅源极/漏极延伸部分基本上相同的掺杂剂浓度下。随后的处理包括沉积间隔层，蚀刻以形成侧壁间隔物，离子注入以形成深度中等或重的源/漏植入物和活化退火。

20. 发明授权

US08835233B2 FinFET structure with multiple workfunctions and method for fabricating the same 有权
标题翻译：具有多种功能的FinFET结构及其制造方法
公开(公告)号：US08835233B2
公开(公告)日：2014-09-16
申请号：US13539727
申请日：2012-07-02
申请人： Andy C. Wei , Akshey Sehgal , Bamidele S. Allimi
发明人： Andy C. Wei , Akshey Sehgal , Bamidele S. Allimi
IPC分类号： H01L21/84
CPC分类号： H01L21/823821 , H01L29/66545
摘要： A method for fabricating a multiple-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure and etching the first workfunction material layer so as to completely remove the first workfunction material layer from all but a first trench of the plurality of trenches. Further, the method includes depositing a second workfunction material in a layer in the plurality of trenches and etching the second workfunction material layer so as to completely remove the second workfunction material layer from all but a second trench of the plurality of trenches. Still further, the method includes depositing a third workfunction material in a layer in the plurality of trenches.
摘要翻译：一种用于制造多功能FinFET结构的方法，包括：在FinFET结构的多个沟槽中的层中沉积第一功函数材料，并蚀刻第一功函数材料层，以从第一功函数材料层中除去第一功函数材料层多个沟槽的沟槽。此外，所述方法包括在所述多个沟槽中的层中沉积第二功函数材料并蚀刻所述第二功函数材料层，以便从所述多个沟槽中的所有除第二沟槽以外的全部除去所述第二功函数材料层。此外，该方法包括在多个沟槽中的层中沉积第三功函数材料。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式