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1. 发明授权

US08557666B2 Methods for fabricating integrated circuits 有权
公开(公告)号：US08557666B2
公开(公告)日：2013-10-15
申请号：US13231750
申请日：2011-09-13
申请人： Andy C. Wei , Peter Baars , Erik P. Geiss
发明人： Andy C. Wei , Peter Baars , Erik P. Geiss
IPC分类号： H01L21/336
CPC分类号： H01L21/823418 , H01L21/76224 , H01L21/76897 , H01L21/823431 , H01L21/823821 , H01L29/41783 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

2. 发明申请

US20130065371A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS 有权
标题翻译：制作集成电路的方法
公开(公告)号：US20130065371A1
公开(公告)日：2013-03-14
申请号：US13231750
申请日：2011-09-13
申请人： Andy C. Wei , Peter Baars , Erik P. Geiss
发明人： Andy C. Wei , Peter Baars , Erik P. Geiss
IPC分类号： H01L21/336 , H01L21/762 , H01L21/20
CPC分类号： H01L21/823418 , H01L21/76224 , H01L21/76897 , H01L21/823431 , H01L21/823821 , H01L29/41783 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.
摘要翻译：提供了用于制造集成电路的方法。一种方法包括将多个沟槽蚀刻成硅衬底并用绝缘材料填充沟槽以描绘多个间隔开的硅片。外延生长一层未掺杂的硅以形成翅片的上部未掺杂区域。虚拟门结构形成为覆盖并横向于多个翅片，并且后填充材料填充在虚拟栅极结构之间。去除虚拟栅极结构以暴露一部分散热片，并且将高k电介质材料和确定栅极电极材料的功函数沉积在鳍片的该部分上。去除后填充材料以暴露第二部分，并且在第二部分上形成金属硅化物接触。然后，将导电触点形成到功函数确定材料和金属硅化物。

3. 发明申请

US20130137269A1 PATTERNING METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件的方法
公开(公告)号：US20130137269A1
公开(公告)日：2013-05-30
申请号：US13307079
申请日：2011-11-30
申请人： Erik P. Geiss , Peter Baars
发明人： Erik P. Geiss , Peter Baars
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/76816 , H01L21/76895 , H01L21/76897
摘要： A patterning method is provided for fabrication of a semiconductor device structure having conductive contact elements, an interlayer dielectric material overlying the contact elements, an organic planarization layer overlying the interlayer dielectric material, an antireflective coating material overlying the organic planarization layer, and a photoresist material overlying the antireflective coating material. The method creates a patterned photoresist layer from the photoresist material to define oversized openings corresponding to respective conductive contact elements. The antireflective coating is etched using the patterned photoresist as an etch mask. A liner material is deposited overlying the patterned antireflective coating layer. The liner material is etched to create sidewall features, which are used as a portion of an etch mask to form contact recesses for the conductive contact elements.
摘要翻译：提供了一种用于制造具有导电接触元件的半导体器件结构，覆盖接触元件的层间绝缘材料，覆盖在层间电介质材料上的有机平坦化层，覆盖有机平坦化层的抗反射涂层材料和光刻胶材料的图案化方法覆盖抗反射涂层材料。该方法从光致抗蚀剂材料形成图案化的光致抗蚀剂层，以限定对应于各个导电接触元件的超大开孔。使用图案化的光致抗蚀剂作为蚀刻掩模蚀刻抗反射涂层。将衬垫材料沉积在图案化的抗反射涂层上。衬里材料被蚀刻以产生侧壁特征，其被用作蚀刻掩模的一部分以形成用于导电接触元件的接触凹部。

4. 发明申请

US20130193489A1 INTEGRATED CIRCUITS INCLUDING COPPER LOCAL INTERCONNECTS AND METHODS FOR THE MANUFACTURE THEREOF 审中-公开
标题翻译：集成电路，包括铜线互连及其制造方法
公开(公告)号：US20130193489A1
公开(公告)日：2013-08-01
申请号：US13361644
申请日：2012-01-30
申请人： Peter Baars , Erik P. Geiss
发明人： Peter Baars , Erik P. Geiss
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76895 , H01L21/28518 , H01L21/76808 , H01L21/76814 , H01L21/76816 , H01L27/0207 , H01L27/11
摘要： Embodiments of a method for manufacturing an integrated circuit are provided. In one embodiment, a partially-fabricated integrated circuit is produced including a semiconductor substrate having source/drain regions, and a plurality of transistors including a plurality of gate conductors formed over the semiconductor substrate and between the source/drain regions. Device-level contacts are formed in ohmic contact with the gate conductors and with the source/drain regions. The device-level contacts terminate at substantially the same level above the semiconductor substrate. Copper interconnect lines are then formed in a level above the device-level contacts and in ohmic contact therewith to locally interconnect the plurality of transistors.
摘要翻译：提供了一种用于制造集成电路的方法的实施例。在一个实施例中，制造了部分制造的集成电路，其包括具有源极/漏极区域的半导体衬底，以及包括形成在半导体衬底之上和源极/漏极区域之间的多个栅极导体的多个晶体管。器件级触点形成为与栅极导体和源极/漏极区域欧姆接触。器件级触点在半导体衬底上方基本相同的水平处终止。然后，铜互连线形成在器件级触点上方并与其欧姆接触，以局部地互连多个晶体管。

5. 发明授权

US08592302B2 Patterning method for fabrication of a semiconductor device 有权
标题翻译：用于制造半导体器件的图案化方法
公开(公告)号：US08592302B2
公开(公告)日：2013-11-26
申请号：US13307079
申请日：2011-11-30
申请人： Erik P. Geiss , Peter Baars
发明人： Erik P. Geiss , Peter Baars
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/76816 , H01L21/76895 , H01L21/76897
摘要： A patterning method is provided for fabrication of a semiconductor device structure having conductive contact elements, an interlayer dielectric material overlying the contact elements, an organic planarization layer overlying the interlayer dielectric material, an antireflective coating material overlying the organic planarization layer, and a photoresist material overlying the antireflective coating material. The method creates a patterned photoresist layer from the photoresist material to define oversized openings corresponding to respective conductive contact elements. The antireflective coating is etched using the patterned photoresist as an etch mask. A liner material is deposited overlying the patterned antireflective coating layer. The liner material is etched to create sidewall features, which are used as a portion of an etch mask to form contact recesses for the conductive contact elements.
摘要翻译：提供了一种用于制造具有导电接触元件的半导体器件结构，覆盖接触元件的层间绝缘材料，覆盖在层间电介质材料上的有机平坦化层，覆盖有机平坦化层的抗反射涂层材料和光刻胶材料的图案化方法覆盖抗反射涂层材料。该方法从光致抗蚀剂材料形成图案化的光致抗蚀剂层，以限定对应于各个导电接触元件的超大开孔。使用图案化的光致抗蚀剂作为蚀刻掩模蚀刻抗反射涂层。将衬垫材料沉积在图案化的抗反射涂层上。衬里材料被蚀刻以产生侧壁特征，其被用作蚀刻掩模的一部分以形成用于导电接触元件的接触凹部。

6. 发明申请

US20100327412A1 METHOD OF SEMICONDUCTOR MANUFACTURING FOR SMALL FEATURES 有权
标题翻译：小功能半导体制造方法
公开(公告)号：US20100327412A1
公开(公告)日：2010-12-30
申请号：US12494015
申请日：2009-06-29
申请人： Doug H. Lee , Erik P. Geiss
发明人： Doug H. Lee , Erik P. Geiss
IPC分类号： H01L29/06 , B44C1/22 , H01L21/467
CPC分类号： H01L21/0337
摘要： Small feature patterning is accomplished using a multilayer hard mask (HM). Embodiments include sequentially forming a first HM layer and a multilayer HM layer over a substrate, the multilayer HM layer comprising sublayers, etching the multilayer HM layer to form a first opening having an upper first opening with sides converging to a lower second opening and a second opening with substantially parallel sides and an opening substantially corresponding to the lower second opening of the first opening, etching through the second opening to form a corresponding opening in the first HM layer, and etching the substrate through the corresponding opening in the first HM layer.
摘要翻译：使用多层硬掩模（HM）实现小特征图案化。实施例包括在衬底上顺序地形成第一HM层和多层HM层，所述多层HM层包括子层，蚀刻多层HM层以形成具有上部第一开口的第一开口，其侧边会聚到较低的第二开口，开口具有基本上平行的侧面和基本上对应于第一开口的下部第二开口的开口，蚀刻穿过第二开口以在第一HM层中形成对应的开口，以及通过第一HM层中的相应开口蚀刻衬底。

7. 发明授权

US08071485B2 Method of semiconductor manufacturing for small features 有权
标题翻译：小功能的半导体制造方法
公开(公告)号：US08071485B2
公开(公告)日：2011-12-06
申请号：US12494015
申请日：2009-06-29
申请人： Doug H. Lee , Erik P. Geiss
发明人： Doug H. Lee , Erik P. Geiss
IPC分类号： H01L21/461
CPC分类号： H01L21/0337
摘要： Small feature patterning is accomplished using a multilayer hard mask (HM). Embodiments include sequentially forming a first HM layer and a multilayer HM layer over a substrate, the multilayer HM layer comprising sublayers, etching the multilayer HM layer to form a first opening having an upper first opening with sides converging to a lower second opening and a second opening with substantially parallel sides and an opening substantially corresponding to the lower second opening of the first opening, etching through the second opening to form a corresponding opening in the first HM layer, and etching the substrate through the corresponding opening in the first HM layer.
摘要翻译：使用多层硬掩模（HM）实现小特征图案化。实施例包括在衬底上顺序地形成第一HM层和多层HM层，所述多层HM层包括子层，蚀刻多层HM层以形成具有上部第一开口的第一开口，其侧边会聚到较低的第二开口，开口具有基本上平行的侧面和基本上对应于第一开口的下部第二开口的开口，蚀刻穿过第二开口以在第一HM层中形成对应的开口，以及通过第一HM层中的相应开口蚀刻衬底。

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