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11. 发明申请

US20100308418A1 Semiconductor Devices and Methods of Manufacture Thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100308418A1
公开(公告)日：2010-12-09
申请号：US12481373
申请日：2009-06-09
申请人： Knut Stahrenberg , Roland Hampp , Jin-Ping Han , Klaus von Arnim
发明人： Knut Stahrenberg , Roland Hampp , Jin-Ping Han , Klaus von Arnim
IPC分类号： H01L27/088 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/82345 , H01L21/823462 , H01L21/823842
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a gate dielectric and a cap layer disposed over the gate dielectric. The first transistor includes a gate including a metal layer disposed over the cap layer and a semiconductive material disposed over the metal layer. The semiconductor device includes a second transistor in a second region of the workpiece, which includes the gate dielectric and the cap layer disposed over the gate dielectric. The second transistor includes a gate that includes the metal layer disposed over the cap layer and the semiconductive material disposed over the metal layer. A thickness of the metal layer, a thickness of the semiconductive material, an implantation region of a channel region, or a doped region of the gate dielectric of the first transistor achieves a predetermined threshold voltage for the first transistor.
摘要翻译：公开了半导体器件及其制造方法。在一个实施例中，半导体器件包括具有栅极电介质的第一晶体管和设置在栅极电介质上的覆盖层。第一晶体管包括包括设置在盖层上的金属层的栅极和设置在金属层上的半导体材料。半导体器件包括在工件的第二区域中的第二晶体管，其包括设置在栅极电介质上的栅极电介质和盖层。第二晶体管包括栅极，其包括设置在覆盖层上的金属层和设置在金属层上的半导体材料。第一晶体管的金属层的厚度，半导体材料的厚度，沟道区的注入区域或栅极电介质的掺杂区域实现了第一晶体管的预定阈值电压。

12. 发明申请

US20090032841A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090032841A1
公开(公告)日：2009-02-05
申请号：US11832449
申请日：2007-08-01
申请人： Manfred Eller , Jin-Ping Han
发明人： Manfred Eller , Jin-Ping Han
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片上形成栅极电介质，并在栅极电介质上形成栅极。至少一个凹部形成在靠近栅极和栅极电介质的半导体晶片中，至少一个凹部的至少一部分在栅极下方延伸。半导体晶片中的至少一个凹部填充有半导体材料。

13. 发明申请

US20080076214A1 Semiconductor device and method of making same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080076214A1
公开(公告)日：2008-03-27
申请号：US11526499
申请日：2006-09-25
申请人： Jin-Ping Han , Haoren Zhuang , Jiang Yan , Jingyu Lian , Manfred Eller
发明人： Jin-Ping Han , Haoren Zhuang , Jiang Yan , Jingyu Lian , Manfred Eller
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/28017 , H01L21/28123 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L21/82385 , H01L29/42364 , H01L29/42368 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/66575 , H01L29/66636 , H01L29/78
摘要： A method of making a semiconductor device is disclosed. A device is fabricated on a semiconductor body. A gate electrode is disposed over the semiconductor body with a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric has a length greater than the gate electrode. A first source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the first source/drain region, and a second source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the second source/drain region.
摘要翻译：公开了制造半导体器件的方法。器件制造在半导体主体上。栅电极设置在半导体本体上，在栅电极和半导体本体之间具有栅极电介质，其中栅极电介质具有大于栅电极的长度。第一源极/漏极区域设置在与栅极的第一边缘相邻的半导体本体内，栅极电介质至少部分地与第一源极/漏极区域重叠，并且第二源极/漏极区域设置在与半导体本体相邻的第二源极/漏极区域内具有栅极电介质的栅极的第一边缘至少部分地与第二源极/漏极区重叠。

14. 发明授权

US09209088B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09209088B2
公开(公告)日：2015-12-08
申请号：US11832449
申请日：2007-08-01
申请人： Manfred Eller , Jin-Ping Han
发明人： Manfred Eller , Jin-Ping Han
IPC分类号： H01L21/3205 , H01L21/8238 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片上形成栅极电介质，并在栅极电介质上形成栅极。至少一个凹部形成在靠近栅极和栅极电介质的半导体晶片中，至少一个凹部的至少一部分在栅极下方延伸。半导体晶片中的至少一个凹部填充有半导体材料。

15. 发明授权

US09070759B2 Semiconductor device and method of making same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09070759B2
公开(公告)日：2015-06-30
申请号：US11526499
申请日：2006-09-25
申请人： Jin-Ping Han , Haoren Zhuang , Jiang Yan , Jingyu Lian , Manfred Eller
发明人： Jin-Ping Han , Haoren Zhuang , Jiang Yan , Jingyu Lian , Manfred Eller
IPC分类号： H01L21/336 , H01L21/311 , H01L29/51 , H01L29/78 , H01L29/423 , H01L21/28 , H01L29/49 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/4983 , H01L21/28017 , H01L21/28123 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L21/82385 , H01L29/42364 , H01L29/42368 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/66575 , H01L29/66636 , H01L29/78
摘要： A method of making a semiconductor device is disclosed. A device is fabricated on a semiconductor body. A gate electrode is disposed over the semiconductor body with a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric has a length greater than the gate electrode. A first source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the first source/drain region, and a second source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the second source/drain region.
摘要翻译：公开了制造半导体器件的方法。器件制造在半导体主体上。栅电极设置在半导体本体上，在栅电极和半导体本体之间具有栅极电介质，其中栅极电介质具有大于栅电极的长度。第一源极/漏极区域设置在与栅极的第一边缘相邻的半导体本体内，栅极电介质至少部分地与第一源极/漏极区域重叠，并且第二源极/漏极区域设置在与半导体本体相邻的第二源极/漏极区域内具有栅极电介质的栅极的第一边缘至少部分地与第二源极/漏极区重叠。

16. 发明授权

US07820518B2 Transistor fabrication methods and structures thereof 有权
标题翻译：晶体管制造方法及其结构
公开(公告)号：US07820518B2
公开(公告)日：2010-10-26
申请号：US12129510
申请日：2008-05-29
申请人： Manfred Eller , Jiang Yan , Jin-Ping Han , Alois Gutmann
发明人： Manfred Eller , Jiang Yan , Jin-Ping Han , Alois Gutmann
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-inducing material over the gate, the gate dielectric, and the workpiece. Sidewall spacers are formed from the stress-inducing material on sidewalls of the gate and the gate dielectric.
摘要翻译：公开了制造晶体管和半导体器件的方法及其结构。在一个实施例中，制造晶体管的方法包括在工件上形成栅极电介质，在栅极电介质上形成栅极，并在栅极，栅极电介质和工件上形成应力诱发材料。侧壁间隔物由栅极和栅极电介质的侧壁上的应力诱导材料形成。

17. 发明申请

US20090294866A1 Transistor Fabrication Methods and Structures Thereof 有权
标题翻译：晶体管制造方法及结构
公开(公告)号：US20090294866A1
公开(公告)日：2009-12-03
申请号：US12129510
申请日：2008-05-29
申请人： Manfred Eller , Jiang Yan , Jin-Ping Han , Alois Gutmann
发明人： Manfred Eller , Jiang Yan , Jin-Ping Han , Alois Gutmann
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-inducing material over the gate, the gate dielectric, and the workpiece. Sidewall spacers are formed from the stress-inducing material on sidewalls of the gate and the gate dielectric.
摘要翻译：公开了制造晶体管和半导体器件的方法及其结构。在一个实施例中，制造晶体管的方法包括在工件上形成栅极电介质，在栅极电介质上形成栅极，并在栅极，栅极电介质和工件上形成应力诱发材料。侧壁间隔物由栅极和栅极电介质的侧壁上的应力诱导材料形成。

18. 发明申请

US20110006373A1 Transistor Structure 审中-公开
标题翻译：晶体管结构
公开(公告)号：US20110006373A1
公开(公告)日：2011-01-13
申请号：US12884417
申请日：2010-09-17
申请人： Manfred Eller , Jiang Yan , Jin-Ping Han , Alois Gutmann
发明人： Manfred Eller , Jiang Yan , Jin-Ping Han , Alois Gutmann
IPC分类号： H01L27/092 , H01L27/088
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-inducing material over the gate, the gate dielectric, and the workpiece. Sidewall spacers are formed from the stress-inducing material on sidewalls of the gate and the gate dielectric.
摘要翻译：公开了制造晶体管和半导体器件的方法及其结构。在一个实施例中，制造晶体管的方法包括在工件上形成栅极电介质，在栅极电介质上形成栅极，并在栅极，栅极电介质和工件上形成应力诱发材料。侧壁间隔物由栅极和栅极电介质的侧壁上的应力诱导材料形成。

19. 发明授权

US08106462B2 Balancing NFET and PFET performance using straining layers 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US08106462B2
公开(公告)日：2012-01-31
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

20. 发明授权

US08063449B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08063449B2
公开(公告)日：2011-11-22
申请号：US12626496
申请日：2009-11-25
申请人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
发明人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。在衬套上形成填充材料。填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

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