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1. 发明申请

US20100155854A1 Methods of Fabricating Semiconductor Devices and Structures Thereof 有权
标题翻译：制造半导体器件及其结构的方法
公开(公告)号：US20100155854A1
公开(公告)日：2010-06-24
申请号：US12341542
申请日：2008-12-22
申请人： Knut Stahrenberg , Jin-Ping Han
发明人： Knut Stahrenberg , Jin-Ping Han
IPC分类号： H01L21/28 , H01L27/088
CPC分类号： H01L21/28088 , H01L21/2822 , H01L21/28229 , H01L21/82345 , H01L21/823462 , H01L21/823828 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L29/401 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/78
摘要： Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. A composition or a thickness of at least one of a plurality of material layers of the gate material stack is altered in at least the second region. The gate material stack is patterned, forming a first transistor in the first region and forming a second transistor in the second region. Altering the composition or the thickness of the at least one of the plurality of material layers of the gate material stack in at least the second region results in a first transistor having a first threshold voltage and a second transistor having a second threshold voltage, the second threshold voltage having a different magnitude than the first threshold voltage.
摘要翻译：公开了制造半导体器件的方法及其结构。在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的工件上形成栅极材料堆叠。至少在第二区域中改变栅极材料层叠的多个材料层中的至少一个的组成或厚度。图案化栅极材料堆叠，在第一区域中形成第一晶体管，并在第二区域中形成第二晶体管。在至少第二区域中改变栅极材料堆叠的多个材料层中的至少一个材料层的组成或厚度导致具有第一阈值电压的第一晶体管和具有第二阈值电压的第二晶体管，第二晶体管具有第二阈值电压阈值电压具有与第一阈值电压不同的幅度。

2. 发明申请

US20120319208A1 Methods of Fabricating Semiconductor Devices and Structures Thereof 有权
标题翻译：制造半导体器件及其结构的方法
公开(公告)号：US20120319208A1
公开(公告)日：2012-12-20
申请号：US13588431
申请日：2012-08-17
申请人： Knut Stahrenberg , Jin-Ping Han
发明人： Knut Stahrenberg , Jin-Ping Han
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L21/28088 , H01L21/2822 , H01L21/28229 , H01L21/82345 , H01L21/823462 , H01L21/823828 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L29/401 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/78
摘要： Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. A composition or a thickness of at least one of a plurality of material layers of the gate material stack is altered in at least the second region. The gate material stack is patterned, forming a first transistor in the first region and forming a second transistor in the second region. Altering the composition or the thickness of the at least one of the plurality of material layers of the gate material stack in at least the second region results in a first transistor having a first threshold voltage and a second transistor having a second threshold voltage, the second threshold voltage having a different magnitude than the first threshold voltage.
摘要翻译：公开了制造半导体器件的方法及其结构。在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的工件上形成栅极材料堆叠。至少在第二区域中改变栅极材料层叠的多个材料层中的至少一个的组成或厚度。图案化栅极材料堆叠，在第一区域中形成第一晶体管，并在第二区域中形成第二晶体管。在至少第二区域中改变栅极材料堆叠的多个材料层中的至少一个材料层的组成或厚度导致具有第一阈值电压的第一晶体管和具有第二阈值电压的第二晶体管，第二晶体管具有第二阈值电压阈值电压具有与第一阈值电压不同的幅度。

3. 发明申请

US20110175174A1 Methods of Manufacturing Resistors and Structures Thereof 审中-公开
标题翻译：制造电阻器及其结构的方法
公开(公告)号：US20110175174A1
公开(公告)日：2011-07-21
申请号：US13077554
申请日：2011-03-31
申请人： Knut Stahrenberg , Jin-Ping Han
发明人： Knut Stahrenberg , Jin-Ping Han
IPC分类号： H01L29/772
CPC分类号： H01L27/0629 , H01L21/823814 , H01L28/20
摘要： A semiconductor device includes a semiconductor body of a first semiconductive material. A transistor is disposed in the semiconductor body. The transistor includes source and drain regions of a second semiconductive material embedded in the semiconductor body. A resistor overlies a top surface of the semiconductor body and is laterally spaced from the transistor. The resistor is formed from the second semiconductive material.
摘要翻译：半导体器件包括第一半导体材料的半导体本体。晶体管设置在半导体本体中。晶体管包括嵌入半导体本体中的第二半导体材料的源区和漏区。电阻器覆盖半导体主体的顶表面并与晶体管横向间隔开。电阻器由第二半导体材料形成。

4. 发明授权

US07091083B2 Method for producing a capacitor 有权
标题翻译：电容器的制造方法
公开(公告)号：US07091083B2
公开(公告)日：2006-08-15
申请号：US10888574
申请日：2004-07-09
申请人： Claus Dahl , Knut Stahrenberg , Christoph Wilbertz
发明人： Claus Dahl , Knut Stahrenberg , Christoph Wilbertz
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , H01L21/28525 , H01L27/0805 , H01L29/94
摘要： A method for producing a capacitor comprises providing a raw structure having a substrate and at least one dielectric layer, wherein a first area and a second area of the substrate are separated by an isolating layer. Above the first and second areas, an electrically conductive layer is arranged on the at least one dielectric layer. Further, a mask layer is deposited on the electrically conductive layer, wherein it is structured for generating a first mask above the first area. The method further comprises etching away the electrically conductive layer and at least one of the dielectric layers in the second area by means of the first mask and completing an active device in the second area.
摘要翻译：制造电容器的方法包括提供具有基底和至少一个电介质层的原始结构，其中基底的第一区域和第二区域被隔离层隔开。在第一和第二区域之上，导电层设置在至少一个电介质层上。此外，掩模层沉积在导电层上，其中其被构造用于在第一区域上方产生第一掩模。该方法还包括通过第一掩模蚀刻掉第二区域中的导电层和介电层中的至少一个，并在第二区域中完成有源器件。

5. 发明申请

US20050037591A1 Method for producing a capacitor 有权
标题翻译：电容器的制造方法
公开(公告)号：US20050037591A1
公开(公告)日：2005-02-17
申请号：US10888574
申请日：2004-07-09
申请人： Claus Dahl , Knut Stahrenberg , Christoph Wilbertz
发明人： Claus Dahl , Knut Stahrenberg , Christoph Wilbertz
IPC分类号： H01L21/02 , H01L21/285 , H01L27/08 , H01L29/94 , H01L21/20
CPC分类号： H01L28/60 , H01L21/28525 , H01L27/0805 , H01L29/94
摘要： A method for producing a capacitor comprises providing a raw structure having a substrate and at least one dielectric layer, wherein a first area and a second area of the substrate are separated by an isolating layer. Above the first and second areas, an electrically conductive layer is arranged on the at least one dielectric layer. Further, a mask layer is deposited on the electrically conductive layer, wherein it is structured for generating a first mask above the first area. The method further comprises etching away the electrically conductive layer and at least one of the dielectric layers in the second area by means of the first mask and completing an active device in the second area.
摘要翻译：制造电容器的方法包括提供具有基底和至少一个电介质层的原始结构，其中基底的第一区域和第二区域被隔离层隔开。在第一和第二区域之上，导电层设置在至少一个电介质层上。此外，掩模层沉积在导电层上，其中其被构造用于在第一区域上方产生第一掩模。该方法还包括通过第一掩模蚀刻掉第二区域中的导电层和介电层中的至少一个，并在第二区域中完成有源器件。

6. 发明授权

US09142547B2 Methods of manufacturing resistors and structures thereof 有权
标题翻译：制造电阻器及其结构的方法
公开(公告)号：US09142547B2
公开(公告)日：2015-09-22
申请号：US13077554
申请日：2011-03-31
申请人： Knut Stahrenberg , Jin-Ping Han
发明人： Knut Stahrenberg , Jin-Ping Han
IPC分类号： H01L27/06 , H01L49/02 , H01L21/8238
CPC分类号： H01L27/0629 , H01L21/823814 , H01L28/20
摘要： A semiconductor device includes a semiconductor body of a first semiconductive material. A transistor is disposed in the semiconductor body. The transistor includes source and drain regions of a second semiconductive material embedded in the semiconductor body. A resistor overlies a top surface of the semiconductor body and is laterally spaced from the transistor. The resistor is formed from the second semiconductive material.
摘要翻译：半导体器件包括第一半导体材料的半导体本体。晶体管设置在半导体本体中。晶体管包括嵌入半导体本体中的第二半导体材料的源区和漏区。电阻器覆盖半导体主体的顶表面并与晶体管横向间隔开。电阻器由第二半导体材料形成。

7. 发明申请

US20100308418A1 Semiconductor Devices and Methods of Manufacture Thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100308418A1
公开(公告)日：2010-12-09
申请号：US12481373
申请日：2009-06-09
申请人： Knut Stahrenberg , Roland Hampp , Jin-Ping Han , Klaus von Arnim
发明人： Knut Stahrenberg , Roland Hampp , Jin-Ping Han , Klaus von Arnim
IPC分类号： H01L27/088 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/82345 , H01L21/823462 , H01L21/823842
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a gate dielectric and a cap layer disposed over the gate dielectric. The first transistor includes a gate including a metal layer disposed over the cap layer and a semiconductive material disposed over the metal layer. The semiconductor device includes a second transistor in a second region of the workpiece, which includes the gate dielectric and the cap layer disposed over the gate dielectric. The second transistor includes a gate that includes the metal layer disposed over the cap layer and the semiconductive material disposed over the metal layer. A thickness of the metal layer, a thickness of the semiconductive material, an implantation region of a channel region, or a doped region of the gate dielectric of the first transistor achieves a predetermined threshold voltage for the first transistor.
摘要翻译：公开了半导体器件及其制造方法。在一个实施例中，半导体器件包括具有栅极电介质的第一晶体管和设置在栅极电介质上的覆盖层。第一晶体管包括包括设置在盖层上的金属层的栅极和设置在金属层上的半导体材料。半导体器件包括在工件的第二区域中的第二晶体管，其包括设置在栅极电介质上的栅极电介质和盖层。第二晶体管包括栅极，其包括设置在覆盖层上的金属层和设置在金属层上的半导体材料。第一晶体管的金属层的厚度，半导体材料的厚度，沟道区的注入区域或栅极电介质的掺杂区域实现了第一晶体管的预定阈值电压。

8. 发明申请

US20100148262A1 Resistors and Methods of Manufacture Thereof 审中-公开
标题翻译：电阻器及其制造方法
公开(公告)号：US20100148262A1
公开(公告)日：2010-06-17
申请号：US12336702
申请日：2008-12-17
申请人： Knut Stahrenberg , Karl-Heinz Bach , Manfred Eller , Roland Hampp , Jin-Ping Han , O Sung Kwon
发明人： Knut Stahrenberg , Karl-Heinz Bach , Manfred Eller , Roland Hampp , Jin-Ping Han , O Sung Kwon
IPC分类号： H01L29/772 , H01L21/02
CPC分类号： H01L28/20 , H01L27/0629
摘要： Resistors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a semiconductive material over a workpiece, and patterning at least the semiconductive material, forming a gate of a transistor in a first region of the workpiece and forming a resistor in a second region of the workpiece. At least one substance is implanted into the semiconductive material of the gate of the transistor or the resistor so that the semiconductive material is different for the gate of the transistor and the resistor.
摘要翻译：公开了电阻器，半导体器件及其制造方法。在一个实施例中，制造电阻器的方法包括在工件上形成半导体材料，并且至少构图半导体材料，在工件的第一区域中形成晶体管的栅极，并在第二区域中形成电阻器工件。将至少一种物质注入到晶体管或电阻器的栅极的半导体材料中，使得半导体材料对于晶体管和电阻器的栅极是不同的。

9. 发明授权

US08432014B2 Methods of fabricating semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的方法及其结构
公开(公告)号：US08432014B2
公开(公告)日：2013-04-30
申请号：US13588431
申请日：2012-08-17
申请人： Knut Stahrenberg , Jin-Ping Han
发明人： Knut Stahrenberg , Jin-Ping Han
IPC分类号： H01L21/70
CPC分类号： H01L21/28088 , H01L21/2822 , H01L21/28229 , H01L21/82345 , H01L21/823462 , H01L21/823828 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L29/401 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/78
摘要： Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. A composition or a thickness of at least one of a plurality of material layers of the gate material stack is altered in at least the second region. The gate material stack is patterned, forming a first transistor in the first region and forming a second transistor in the second region. Altering the composition or the thickness of the at least one of the plurality of material layers of the gate material stack in at least the second region results in a first transistor having a first threshold voltage and a second transistor having a second threshold voltage, the second threshold voltage having a different magnitude than the first threshold voltage.
摘要翻译：公开了制造半导体器件的方法及其结构。在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的工件上形成栅极材料堆叠。至少在第二区域中改变栅极材料层叠的多个材料层中的至少一个的组成或厚度。图案化栅极材料堆叠，在第一区域中形成第一晶体管，并在第二区域中形成第二晶体管。在至少第二区域中改变栅极材料堆叠的多个材料层中的至少一个材料层的组成或厚度导致具有第一阈值电压的第一晶体管和具有第二阈值电压的第二晶体管，第二晶体管具有第二阈值电压阈值电压具有与第一阈值电压不同的幅度。

10. 发明授权

US08252649B2 Methods of fabricating semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的方法及其结构
公开(公告)号：US08252649B2
公开(公告)日：2012-08-28
申请号：US12341542
申请日：2008-12-22
申请人： Knut Stahrenberg , Jin-Ping Han
发明人： Knut Stahrenberg , Jin-Ping Han
IPC分类号： H01L21/00
CPC分类号： H01L21/28088 , H01L21/2822 , H01L21/28229 , H01L21/82345 , H01L21/823462 , H01L21/823828 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L29/401 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/78
摘要： Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. A composition or a thickness of at least one of a plurality of material layers of the gate material stack is altered in at least the second region. The gate material stack is patterned, forming a first transistor in the first region and forming a second transistor in the second region. Altering the composition or the thickness of the at least one of the plurality of material layers of the gate material stack in at least the second region results in a first transistor having a first threshold voltage and a second transistor having a second threshold voltage, the second threshold voltage having a different magnitude than the first threshold voltage.
摘要翻译：公开了制造半导体器件的方法及其结构。在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的工件上形成栅极材料堆叠。至少在第二区域中改变栅极材料层叠的多个材料层中的至少一个的组成或厚度。图案化栅极材料堆叠，在第一区域中形成第一晶体管，并在第二区域中形成第二晶体管。在至少第二区域中改变栅极材料堆叠的多个材料层中的至少一个材料层的组成或厚度导致具有第一阈值电压的第一晶体管和具有第二阈值电压的第二晶体管，第二晶体管具有第二阈值电压阈值电压具有与第一阈值电压不同的幅度。

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