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11. 发明授权

US07863149B2 Method for fabricating a capacitor 有权
标题翻译：制造电容器的方法
公开(公告)号：US07863149B2
公开(公告)日：2011-01-04
申请号：US11223800
申请日：2005-09-09
申请人： Srivatsa Kundalgurki , Peter Moll , Dirk Manger , Kristin Schupke , Till Schloesser
发明人： Srivatsa Kundalgurki , Peter Moll , Dirk Manger , Kristin Schupke , Till Schloesser
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer (40).
摘要翻译：在制造包括电极结构（80）的电容器的方法中，辅助层（40）形成在衬底（10）上。确定电极结构（80）的形状的凹部（60）被蚀刻到辅助层（40）中，电容器的电极结构形成在凹部中。作为示例，辅助层可以是半导体层（40）。

12. 发明申请

US20070114616A1 Field effect transistor and method of manufacturing the same 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20070114616A1
公开(公告)日：2007-05-24
申请号：US11287151
申请日：2005-11-23
申请人： Dirk Manger , Till Schloesser
发明人： Dirk Manger , Till Schloesser
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L21/2815 , H01L27/10873 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A field effect transistor, which is arranged in a semiconductor device, comprises a first and a second doped source/drain region, both regions being arranged within a semiconductor substrate on either side of a gate electrode, and a channel region formed within the substrate between both doped source/drain regions beneath said gate electrode. A gate oxide layer is formed upon the semiconductor substrate. The gate electrode contacts a surface of the gate oxide layer and further comprises at least a first and a second conductive layer, wherein the first and second conductive layers are made of materials having different work functions with respect to each other. The first conductive layer contacts the gate oxide layer within a first portion of the surface, and the second conductive layer contacts the gate oxide layer within a second portion of the surface. The first conductive layer is further conductively connected to the second conductive layer.
摘要翻译：布置在半导体器件中的场效应晶体管包括第一和第二掺杂源极/漏极区域，两个区域布置在栅电极的任一侧上的半导体衬底内，以及形成在衬底内的沟道区域在所述栅电极下方的掺杂源/漏区两者。在半导体衬底上形成栅氧化层。栅极电极接触栅极氧化物层的表面，并且还包括至少第一和第二导电层，其中第一和第二导电层由相对于彼此具有不同功函数的材料制成。第一导电层在表面的第一部分内接触栅极氧化物层，并且第二导电层在表面的第二部分内接触栅极氧化物层。第一导电层进一步导电连接到第二导电层。

13. 发明授权

US07141845B2 DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
标题翻译：具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法
公开(公告)号：US07141845B2
公开(公告)日：2006-11-28
申请号：US10898706
申请日：2004-07-23
申请人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
发明人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
IPC分类号： H01L27/108
CPC分类号： H01L27/10867 , H01L27/10841 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.
摘要翻译：每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏极电容的减小以及栅电极和漏电极之间的漏电流较低的源极/漏极区域。用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。单元晶体管的上源/漏区通过接触孔注入而形成。

14. 发明授权

US06932916B2 Semiconductor substrate with trenches of varying depth 失效
标题翻译：具有不同深度的沟槽的半导体衬底
公开(公告)号：US06932916B2
公开(公告)日：2005-08-23
申请号：US10425179
申请日：2003-04-29
申请人： Dirk Manger , Hans-Peter Moll , Till Schloesser
发明人： Dirk Manger , Hans-Peter Moll , Till Schloesser
IPC分类号： H01L21/308 , H01L21/334 , H01L21/762 , H01L21/8242 , B44C1/22 , H01L21/302
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76229 , H01L27/1087 , H01L29/66181
摘要： A method for etching trenches having different depths on a semiconductor substrate includes providing a mask with first and second openings. The first and second openings are located where corresponding first and second trenches are to be etched. A slow-etch region, made of a slow-etch material, is provided above the substrate at a location corresponding to the second opening. When exposed to a selected etchant, the slow-etch material is etched at a rate less than the rate at which the semiconductor substrate is etched when exposed to the selected etchant.
摘要翻译：在半导体衬底上蚀刻具有不同深度的沟槽的方法包括：提供具有第一和第二开口的掩模。第一和第二开口位于相应的第一和第二沟槽将被蚀刻的位置。在对应于第二开口的位置处，在衬底上方设置由缓蚀刻材料制成的缓蚀刻区域。当暴露于所选择的蚀刻剂时，以暴露于所选择的蚀刻剂的半导体衬底被蚀刻的速率小的速率蚀刻慢刻蚀材料。

15. 发明申请

US20080285344A1 Integrated Circuits; Methods for Manufacturing an Integrated Circuit; Memory Modules; Computing Systems 有权
标题翻译：集成电路; 集成电路制造方法内存模块计算系统
公开(公告)号：US20080285344A1
公开(公告)日：2008-11-20
申请号：US11749028
申请日：2007-05-15
申请人： Eike Ruttkowski , Detlev Richter , Michael Specht , Joseph Willer , Dirk Manger , Kenny Oisin , Steffen Meyer , Klaus Knobloch , Holger Moeller , Doris Keitel Schulz , Jan Gutsche , Gert Koebernik , Christoph Friederich
发明人： Eike Ruttkowski , Detlev Richter , Michael Specht , Joseph Willer , Dirk Manger , Kenny Oisin , Steffen Meyer , Klaus Knobloch , Holger Moeller , Doris Keitel Schulz , Jan Gutsche , Gert Koebernik , Christoph Friederich
IPC分类号： G11C11/34 , H01L21/82
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.
摘要翻译：本发明的实施例一般涉及集成电路，用于制造集成电路的方法，存储器模块和计算系统。

16. 发明授权

US07649779B2 Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems 有权
标题翻译：集成电路; 集成电路制造方法; 内存模块; 计算系统
公开(公告)号：US07649779B2
公开(公告)日：2010-01-19
申请号：US11749028
申请日：2007-05-15
申请人： Eike Ruttkowski , Detlev Richter , Michael Specht , Joseph Willer , Dirk Manger , Kenny Oisin , Steffen Meyer , Klaus Knobloch , Holger Moeller , Doris Keitel Schulz , Jan Gutsche , Gert Koebernik , Christoph Friederich
发明人： Eike Ruttkowski , Detlev Richter , Michael Specht , Joseph Willer , Dirk Manger , Kenny Oisin , Steffen Meyer , Klaus Knobloch , Holger Moeller , Doris Keitel Schulz , Jan Gutsche , Gert Koebernik , Christoph Friederich
IPC分类号： G11C16/00
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.
摘要翻译：本发明的实施例一般涉及集成电路，用于制造集成电路的方法，存储器模块和计算系统。

17. 发明授权

US07825031B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07825031B2
公开(公告)日：2010-11-02
申请号：US11855809
申请日：2007-09-14
申请人： Dirk Manger , Rolf Weis , Christoph Noelscher
发明人： Dirk Manger , Rolf Weis , Christoph Noelscher
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76816
摘要： The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step.
摘要翻译：本发明涉及一种制造集成电路的方法，包括提供至少一层的步骤; 执行第一注入步骤，其中在第一入射方向上将颗粒注入所述层中; 执行第二注入步骤，其中在与所述第一入射方向不同的第二入射方向上将颗粒注入所述层中; 执行去除步骤，其中根据由第一和第二植入步骤产生的局部植入剂量部分去除该层。

18. 发明申请

US20090033362A1 Method for Forming a Structure on a Substrate and Device 失效
标题翻译：在基板和设备上形成结构的方法
公开(公告)号：US20090033362A1
公开(公告)日：2009-02-05
申请号：US11831504
申请日：2007-07-31
申请人： Dirk Manger , Stephan Wege , Rolf Weis , Christoph Noelscher
发明人： Dirk Manger , Stephan Wege , Rolf Weis , Christoph Noelscher
IPC分类号： H01R43/00 , H01L21/02 , H01L21/31
CPC分类号： H01L21/266 , H01L21/0332 , H01L21/0337 , H01L21/31111 , H01L21/31144 , H01L21/32134 , H01L21/32135 , H01L21/32137 , H01L21/32139
摘要： In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions.
摘要翻译：一方面，公开了一种在衬底上形成结构的方法。例如，该方法包括形成第一掩模层和第二掩模层，改变第一和第二掩模层的区域中的材料特性，以及基于改质区域形成结构。

19. 发明授权

US07662721B2 Hard mask layer stack and a method of patterning 失效
标题翻译：硬掩模层堆叠和图案化方法
公开(公告)号：US07662721B2
公开(公告)日：2010-02-16
申请号：US11376645
申请日：2006-03-15
申请人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
发明人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
IPC分类号： H01L21/461
CPC分类号： H01L21/32139 , H01L21/0332 , H01L27/105 , H01L27/112
摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
摘要翻译：用于图案化待图案化层的硬掩模层堆叠包括设置在待图案化层的顶部上的碳层，选自设置在碳层顶部上的SiO 2和SiON中的第一层材料和硅层设置在第一层的顶部。图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

20. 发明授权

US06900130B2 Method for locally heating a region in a semiconductor substrate 失效
标题翻译：局部加热半导体衬底区域的方法
公开(公告)号：US06900130B2
公开(公告)日：2005-05-31
申请号：US10612628
申请日：2003-07-02
申请人： Dirk Manger
发明人： Dirk Manger
IPC分类号： C23C16/04 , H01L21/02 , H01L21/285 , H01L21/324 , H01L21/326 , H01L21/334 , H01L21/8242 , H01L21/44
CPC分类号： H01L21/324 , C23C16/047 , H01L21/28525 , H01L21/326 , H01L27/1087 , H01L28/60 , H01L29/66181
摘要： A method is proposed for locally heating a region that is disposed in a substrate. A substrate is provided and at least one region is produced in the substrate with a lower specific resistance than the surrounding substrate. The region is then locally heated by inducing eddy currents by irradiation with electromagnetic energy.
摘要翻译：提出了一种局部加热设置在基板中的区域的方法。提供衬底，并且在衬底中产生比周围衬底低的电阻率的至少一个区域。然后通过用电磁能照射引起涡流来局部加热该区域。

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