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11. 发明申请

US20050133846A1 Deep trench capacitor with buried plate electrode and isolation collar 有权
标题翻译：深沟槽电容器，埋置电极和隔离环
公开(公告)号：US20050133846A1
公开(公告)日：2005-06-23
申请号：US10741203
申请日：2003-12-19
申请人： Thomas Dyer , Chun-Yung Sung , Ravikumar Ramachandran , Ramachandra Divakaruni
发明人： Thomas Dyer , Chun-Yung Sung , Ravikumar Ramachandran , Ramachandra Divakaruni
IPC分类号： H01L21/8242 , H01L29/94 , H01L27/108 , H01L31/119
CPC分类号： H01L27/1087 , H01L29/945
摘要： A deep trench capacitor used in a trench DRAM includes a buried plate and an isolation collar. The deep trench is bottle-shaped, and the isolation collar is formed in upper portion of the wider region of the bottle-shaped trench. The buried plate surrounds the lower portion of the wider part of the bottle-shaped trench, and hemispherical grain polysilicon lines the walls of at least the lower portion of the wider part of the trench. A nitride liner layer lines the inner walls of the oxide collar and prevents diffusion of dopant through the oxide collar into the substrate when the HSG polysilicon and the doped buried plate are formed. The buried plate region is self-aligned to the isolation collar. The depth of the top of the wider part of the bottle shape and the bottom depth of the isolation collar are determined by successive resist deposition and recessing steps.
摘要翻译：在沟槽DRAM中使用的深沟槽电容器包括掩埋板和隔离环。深沟是瓶形的，并且隔离套环形成在瓶形沟槽的较宽区域的上部。掩埋板围绕瓶形沟槽的较宽部分的下部，半球状晶粒多晶硅线路至少沟槽较宽部分的下部的壁。当形成HSG多晶硅和掺杂掩埋板时，氮化物衬垫层线化氧化物环的内壁并防止掺杂剂通过氧化物环到衬底中的扩散。掩埋板区域与隔离套环自对准。通过连续的抗蚀剂沉积和凹陷步骤确定瓶子形状的较宽部分的顶部的深度和隔离环的底部深度。

12. 发明授权

US6060398A Guard cell for etching 失效
标题翻译：保护电池用于蚀刻
公开(公告)号：US6060398A
公开(公告)日：2000-05-09
申请号：US37288
申请日：1998-03-09
申请人： Axel Christoph Brintzinger , Ravikumar Ramachandran , Senthil Kumar Srinivasan
发明人： Axel Christoph Brintzinger , Ravikumar Ramachandran , Senthil Kumar Srinivasan
IPC分类号： H01L21/302 , H01L21/311 , H01L23/525
CPC分类号： H01L21/31144 , H01L21/31116 , H01L23/5256 , H01L2924/0002
摘要： A method and apparatus for protecting a neighboring area that is adjacent to a first area that is to be etched. The method includes creating a guard cell substantially surrounding the first area, but excluding the neighboring area. The guard cell is formed of a material that is substantially selective to the etch process subsequently employed to etch within the first area. After the guard cell is formed, an etch is performed within the first area, while the guard cell prevents etching of the neighboring are outside the guard cell.
摘要翻译：一种用于保护与待蚀刻的第一区域相邻的相邻区域的方法和装置。该方法包括创建基本上围绕第一区域但不包括相邻区域的保护单元。保护电池由对第一区域中随后用于蚀刻的蚀刻工艺基本选择性的材料形成。在形成保护单元之后，在第一区域内执行蚀刻，而保护单元防止相邻的蚀刻在保护单元之外。

13. 发明授权

US5807439A Apparatus and method for improved washing and drying of semiconductor wafers 失效
公开(公告)号：US5807439A
公开(公告)日：1998-09-15
申请号：US939547
申请日：1997-09-29
申请人： Hiroyuki Akatsu , Ravikumar Ramachandran
发明人： Hiroyuki Akatsu , Ravikumar Ramachandran
IPC分类号： H01L21/304 , H01L21/00 , F26B7/00
CPC分类号： H01L21/67028 , H01L21/67023 , Y10S134/902
摘要： Apparatus and method are provided for improved washing and drying of semiconductor wafers utilizing an enhanced "Marangoni effect" flow of liquid off of the wafers for superior prevention of watermarks (water spots) on integrated circuits (ICs) on the wafers. The apparatus includes a housing 12 which may be hermetically sealed, an open-top wash tank 60 within a lower part of the housing, a moveable rack 16 for holding the wafers either in the tank for washing or in an upper part of the housing for drying, apparatus 34 for supplying chilled (near freezing) de-ionized water (DIW) to a lower part of the tank, the DIW flowing within the tank and overflowing the top thereof, a pump 20 for draining overflowing DIW from the housing, and apparatus 40 for supplying to the housing organic vapor such as isopropyl alcohol (IPA) in a dry gas such as nitrogen. During wafer drying operation of the apparatus the pressure within the housing is kept at about one Torr or less.

14. 发明授权

US08629014B2 Replacement metal gate structures for effective work function control 有权
标题翻译：更换金属门结构，实现有效的工作功能控制
公开(公告)号：US08629014B2
公开(公告)日：2014-01-14
申请号：US12885592
申请日：2010-09-20
申请人： Unoh Kwon , Michael P. Chudzik , Ravikumar Ramachandran
发明人： Unoh Kwon , Michael P. Chudzik , Ravikumar Ramachandran
IPC分类号： H01L21/8238 , H01L21/70
CPC分类号： H01L27/0922 , H01L21/823842
摘要： A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures.
摘要翻译：在替换金属栅极方案中沉积阻挡金属层和第一型功函数金属层的堆叠。阻挡金属层可以直接沉积在栅极介电层上。图案化第一型功函数金属层仅存在于第一类场效应晶体管的区域中。第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的势垒金属层上。或者，第一类功函数层可以直接沉积在栅介电层上。图案化阻挡金属层仅存在于第一类场效应晶体管的区域中。第二类型功函数金属层直接沉积在第二类场效应晶体管的区域中的栅介质层上。导电材料填充和平坦化形成双重功能替代栅极结构。

15. 发明授权

US08536656B2 Self-aligned contacts for high k/metal gate process flow 有权
标题翻译：用于高k /金属栅极工艺流程的自对准触点
公开(公告)号：US08536656B2
公开(公告)日：2013-09-17
申请号：US12987221
申请日：2011-01-10
申请人： Ravikumar Ramachandran , Ramachandra Divakaruni , Ying Li
发明人： Ravikumar Ramachandran , Ramachandra Divakaruni , Ying Li
IPC分类号： H01L21/70
CPC分类号： H01L29/401 , H01L21/76895 , H01L21/76897 , H01L29/49 , H01L29/4983 , H01L29/51 , H01L29/66545 , H01L29/6656
摘要： A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.
摘要翻译：提供一种半导体结构，其包括具有位于半导体衬底的表面上的多个栅极叠层的半导体衬底。每个栅极堆叠包括从底部到顶部的高k栅极电介质层，功函数金属层和导电金属。间隔件位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫存在于每个间隔件的上表面上。每个自对准电介质衬垫的底表面存在于半导体金属合金的上表面上。接触金属位于相邻的栅极堆叠之间，并通过自对准电介质衬垫与每个栅极堆叠分离。该结构还包括另一个接触金属，其具有位于接触金属的上表面上且与触头金属的上表面直接接触的部分，以及位于与其中一个栅极叠层的导电金属直接接触的另一部分。还公开了使用替换栅极和非替代栅极方案形成半导体结构的方法。

16. 发明授权

US08450169B2 Replacement metal gate structures providing independent control on work function and gate leakage current 失效
标题翻译：替代金属栅极结构提供对功函数和栅极漏电流的独立控制
公开(公告)号：US08450169B2
公开(公告)日：2013-05-28
申请号：US12954946
申请日：2010-11-29
申请人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
发明人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/49 , H01L29/513 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.
摘要翻译：可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的阻挡金属层上。导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

17. 发明申请

US20120139061A1 Self-Aligned Contact For Replacement Gate Devices 有权
标题翻译：用于替代门装置的自对准触点
公开(公告)号：US20120139061A1
公开(公告)日：2012-06-07
申请号：US12958607
申请日：2010-12-02
申请人： Ravikumar Ramachandran , Ying Li , Richard S. Wise
发明人： Ravikumar Ramachandran , Ying Li , Richard S. Wise
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L29/78 , H01L21/76895 , H01L21/76897 , H01L21/823842 , H01L21/823871 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66606 , H01L29/7833 , H01L29/7843
摘要： A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.
摘要翻译：替代栅极堆叠的导电顶表面通过至少一个蚀刻相对于平坦化介电层的顶表面凹陷。介电覆盖层沉积在平坦化电介质层和替代栅极堆叠的顶表面上，使得替代栅极堆叠上的介电顶盖层的一部分的顶表面相对于上述电介质层的另一部分垂直凹陷平坦化介电层。电介质覆盖层的垂直偏移可以与选择性通孔蚀刻工艺结合使用以形成自对准接触结构。

18. 发明授权

US07943457B2 Dual metal and dual dielectric integration for metal high-k FETs 有权
标题翻译：金属高k FET的双金属和双电介质集成
公开(公告)号：US07943457B2
公开(公告)日：2011-05-17
申请号：US12423236
申请日：2009-04-14
申请人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
发明人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/49 , H01L29/7833
摘要： The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.
摘要翻译：在一个实施例中，本发明提供一种形成半导体器件的方法，该半导体器件包括提供包括第一导电类型区域和第二导电类型区域的衬底; 在所述基板的第一导电类型区域和所述第二导电类型区域之上形成包括栅极电介质的栅极堆叠和覆盖所述高k栅极电介质的第一金属栅极导体; 去除存在于第一导电类型区域中的第一金属栅极导体的一部分以暴露存在于第一导电类型区域中的栅极电介质; 将氮基等离子体施加到所述基板，其中所述氮基等离子体氮化存在于所述第一导电类型区域中的所述栅极电介质，并且氮化所述第二导电类型区域中存在的所述第一金属栅极导体; 以及形成覆盖存在于第一导电类型区域中的至少栅极电介质的第二金属栅极导体。

19. 发明授权

US07335969B2 Method of monitoring introduction of interfacial species 失效
标题翻译：监测界面物种引进方法
公开(公告)号：US07335969B2
公开(公告)日：2008-02-26
申请号：US11076371
申请日：2005-03-09
申请人： Lance Genicola , Mark J. Hurley , Jeremy J. Kempisty , Paul D. Kirsch , Ravikumar Ramachandran , Suri Hedge
发明人： Lance Genicola , Mark J. Hurley , Jeremy J. Kempisty , Paul D. Kirsch , Ravikumar Ramachandran , Suri Hedge
IPC分类号： H01L21/66
CPC分类号： H01L21/67167 , H01L21/02329 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/2822 , H01L21/28238 , H01L21/3144 , H01L21/3185 , H01L21/67213 , H01L21/67253 , H01L29/513 , H01L29/518 , Y10T29/41
摘要： A method for monitoring a nitridation process, including: (a) providing a semiconductor substrate; (b) forming a first dielectric layer on a top surface of the substrate; (c) introducing a quantity of interfacial species into the substrate; (d) removing the first dielectric layer; (e) forming a second dielectric layer on the top surface of the substrate; (f) measuring the density of interface traps between the substrate and the second dielectric layer; (g) providing a predetermined relationship between the quantity of the interfacial species and the density of the interface traps; and (h) determining the quantity of the interfacial species introduced based on the relationship.
摘要翻译：一种用于监测氮化工艺的方法，包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成第一电介质层; （c）将一定量的界面物质引入底物; （d）去除第一电介质层; （e）在所述衬底的顶表面上形成第二电介质层; （f）测量衬底和第二介电层之间的界面陷阱的密度; （g）提供界面物质的量与界面捕集阱的密度之间的预定关系; 和（h）基于关系确定引入的界面物质的数量。

20. 发明授权

US06929964B2 Method of monitoring introduction on interfacial species 失效
标题翻译：监测界面种类介绍的方法
公开(公告)号：US06929964B2
公开(公告)日：2005-08-16
申请号：US10605244
申请日：2003-09-17
申请人： Lance Genicola , Mark J. Hurley , Jeremy J. Kempisty , Paul D. Kirsch , Ravikumar Ramachandran , Suri Hedge
发明人： Lance Genicola , Mark J. Hurley , Jeremy J. Kempisty , Paul D. Kirsch , Ravikumar Ramachandran , Suri Hedge
IPC分类号： H01L21/00 , H01L21/28 , H01L21/314 , H01L21/318 , H01L29/51 , H01L21/66
CPC分类号： H01L21/67167 , H01L21/02329 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/2822 , H01L21/28238 , H01L21/3144 , H01L21/3185 , H01L21/67213 , H01L21/67253 , H01L29/513 , H01L29/518 , Y10T29/41
摘要： A method for monitoring a nitridation process, including: (a) providing a semiconductor substrate; (b) forming a first dielectric layer on a top surface of the substrate; (c) introducing a quantity of interfacial species into the substrate; (d) removing the first dielectric layer; (e) forming a second dielectric layer on the top surface of the substrate; (f) measuring the density of interface traps between the substrate and the second dielectric layer; (g) providing a predetermined relationship between the quantity of the interfacial species and the density of the interface traps; and (h) determining the quantity of the interfacial species introduced based on the relationship.
摘要翻译：一种用于监测氮化工艺的方法，包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成第一电介质层; （c）将一定量的界面物质引入底物; （d）去除第一电介质层; （e）在所述衬底的顶表面上形成第二电介质层; （f）测量衬底和第二介电层之间的界面陷阱的密度; （g）提供界面物质的量与界面捕集阱的密度之间的预定关系; 和（h）基于关系确定引入的界面物质的数量。

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