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11. 发明申请

US20090199020A1 METHOD AND SYSTEM OF MULTI-CORE MICROPROCESSOR POWER MANAGEMENT AND CONTROL VIA PER-CHIPLET, PROGRAMMABLE POWER MODES 有权
标题翻译：多芯片微处理器电源管理和控制方法与系统，可编程电源模式
公开(公告)号：US20090199020A1
公开(公告)日：2009-08-06
申请号：US12023536
申请日：2008-01-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171
摘要： A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor. The global power management controller issues commands either directly for a specific chiplet out of the plurality of chiplets or to the plurality of chiplets and the control slave bus translates the command into sub-commands dedicated to specific chiplets within the plurality of chiplets. Each chiplet may be set to separate power levels.
摘要翻译：提供了一种计算机实现的方法和用于管理多核微处理器中的电力的系统。小电流中的电源管理控制微体系结构转换包括功率设置的第一命令。小巧包括处理器核心和相关联的存储器高速缓存。功率管理控制微体系结构包括功率模式寄存器，功率模式调节器，转换器和微架构电源管理技术。电源管理控制微架构根据功率设置设置微体系结构电源管理技术。全球电源管理控制器发出第一个命令。全局功率管理控制器可以驻留在微处理器上或者关闭。全局功率管理控制器直接针对多个小芯片中的特定小时或多个小芯片发出命令，并且控制从总线将命令转换为专用于多个小芯片内的特定小芯片的子命令。每个小穗可以设置为分开的功率水平。

12. 发明授权

US09003218B2 Power shifting in multicore platforms by varying SMT levels 有权
公开(公告)号：US09003218B2
公开(公告)日：2015-04-07
申请号：US13476179
申请日：2012-05-21
申请人： Pradip Bose , Alper Buyuktosunoglu , Dilma Menezes Da Silva , Hubertus Franke , Priyanka Tembey
发明人： Pradip Bose , Alper Buyuktosunoglu , Dilma Menezes Da Silva , Hubertus Franke , Priyanka Tembey
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/3203 , G06F1/329 , G06F9/4893 , G06F9/50 , Y02D10/24
摘要： Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.

13. 发明申请

US20130339762A1 ADAPTIVE WORKLOAD BASED OPTIMIZATIONS TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS 有权
标题翻译：基于自适应工作负载的优化，以减轻集成电路中的当前交付限制
公开(公告)号：US20130339762A1
公开(公告)日：2013-12-19
申请号：US13526230
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F1/26 , G06F9/46 , H03K3/00
CPC分类号： H01L23/00 , G06F11/00 , G06F11/3062 , H01L23/50 , H01L25/065 , H01L2224/16145 , H01L2224/16225
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发节流机制（包括基于令牌的节流），以限制每个C4的当前传输超过预先 - 建立的限制或期限。设计辅助工具用于根据当前交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

14. 发明申请

US20130046955A1 Local Computation Logic Embedded in a Register File to Accelerate Programs 审中-公开
标题翻译：嵌入在寄存器文件中的本地计算逻辑来加速程序
公开(公告)号：US20130046955A1
公开(公告)日：2013-02-21
申请号：US13211701
申请日：2011-08-17
申请人： Pradip Bose , Alper Buyuktosunoglu , Jeffrey Haskell Derby , Michele Martino Franceschini , Robert Kevin Montoye , Augusto J. Vega
发明人： Pradip Bose , Alper Buyuktosunoglu , Jeffrey Haskell Derby , Michele Martino Franceschini , Robert Kevin Montoye , Augusto J. Vega
IPC分类号： G06F15/76
摘要： A system and methods for improving performance of an central processing unit. The central processing unit system includes: a pipeline configured to receive an instruction; and a register file partitioned into a one or more subarrays where (i) the register file includes one or more computation elements and (ii) the one or more computation elements are directly connected to one or more subarrays.
摘要翻译：一种用于提高中央处理单元性能的系统和方法。中央处理单元系统包括：配置成接收指令的流水线; 以及分配到一个或多个子阵列中的寄存器文件，其中（i）寄存器文件包括一个或多个计算元件，并且（ii）一个或多个计算元件直接连接到一个或多个子阵列。

15. 发明申请

US20120245897A1 Virtualized Abstraction with Built-in Data Alignment and Simultaneous Event Monitoring in Performance Counter Based Application Characterization and Tuning 有权
标题翻译：基于性能计数器的应用程序表征和调优的内置数据对齐和同步事件监控的虚拟化抽象
公开(公告)号：US20120245897A1
公开(公告)日：2012-09-27
申请号：US13052616
申请日：2011-03-21
申请人： Pradip Bose , Alper Buyuktosunoglu , Canturk Isci , Jeff Kephart , Xiaoqiao Meng , Ruhi Sarikaya
发明人： Pradip Bose , Alper Buyuktosunoglu , Canturk Isci , Jeff Kephart , Xiaoqiao Meng , Ruhi Sarikaya
IPC分类号： G06F11/30 , G06F15/00
CPC分类号： G06F11/3089 , G06F11/3024 , G06F11/3466 , G06F2201/815 , G06F2201/86 , G06F2201/88
摘要： Techniques for monitoring a set of one or more event counters of application execution are provided. The techniques include constructing a virtual performance monitoring counter (VPMC) layer as a unified abstraction of a physical performance monitoring counter (PMC) architecture, and incorporating one or more programming interfaces (PIs) in connection with the virtual performance monitoring counter, wherein the one or more programming interfaces facilitate simultaneous access and data monitoring across a set of one or more event counters.
摘要翻译：提供了用于监视应用执行的一个或多个事件计数器的集合的技术。这些技术包括构建虚拟性能监视计数器（VPMC）层作为物理性能监视计数器（PMC）体系结构的统一抽象，并且结合一个或多个与虚拟性能监视计数器结合的编程接口（PI），其中一个或更多的编程接口便于跨一组或多个事件计数器的同时访问和数据监视。

16. 发明授权

US08219834B2 Predictive power gating with optional guard mechanism 有权
标题翻译：具有可选保护机构的预测电源门控
公开(公告)号：US08219834B2
公开(公告)日：2012-07-10
申请号：US12539978
申请日：2009-08-12
申请人： Jayanta Basak , Pradip Bose , Alper Buyuktosunoglu , Anita Lungu
发明人： Jayanta Basak , Pradip Bose , Alper Buyuktosunoglu , Anita Lungu
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203
摘要： A mechanism is provided for predictively power gating a set of units within the data processing system. A second-level power gating controller monitors a set of events for each unit in a set of units within the data processing system. The second-level power gating controller identifies idle sequences of a predetermined set of cycles within the events from each unit where the unit is idle. The second-level power gating controller determines preceding sequences of a predetermined length that precede the idle sequences. The second-level power gating controller determines an accuracy of the preceding sequences. Responsive to the accuracy being above a threshold, the second-level power gating controller sends a permit command to a first-level power gating mechanism associated with the unit to permit power gating of the unit.
摘要翻译：提供了用于在数据处理系统内预测性地选通一组单元的机构。二级电源门控控制器监视数据处理系统内的一组单元中的每个单元的一组事件。第二级电力门控控制器从单元空闲的每个单元的事件内识别预定的一组周期的空闲序列。第二级电源门控控制器确定在空闲序列之前的预定长度的先前序列。二级电源门控控制器确定前面的序列的精度。响应于精度高于阈值，二级电源门控控制器向与该单元相关联的一级电源门控机构发送许可命令，以允许该单元的电源门控。

17. 发明授权

US07930578B2 Method and system of peak power enforcement via autonomous token-based control and management 有权
标题翻译：通过自主的基于令牌的控制和管理来实现峰值功率的方法和系统
公开(公告)号：US07930578B2
公开(公告)日：2011-04-19
申请号：US11862559
申请日：2007-09-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
IPC分类号： G06F1/00 , G06F11/30 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3287 , G06F1/206 , G06F9/3836 , G06F9/3869 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D50/20
摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.
摘要翻译：一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率基于系统中分配的令牌总数的消耗限制。

18. 发明授权

US07487012B2 Methods for thermal management of three-dimensional integrated circuits 失效
标题翻译：三维集成电路热管理方法
公开(公告)号：US07487012B2
公开(公告)日：2009-02-03
申请号：US11747279
申请日：2007-05-11
申请人： Pradip Bose , Alper Buyuktosunoglu , Eren Kursun
发明人： Pradip Bose , Alper Buyuktosunoglu , Eren Kursun
IPC分类号： G05D23/00
CPC分类号： G05D23/1932
摘要： A method of dynamic thermal management in a multi-dimensional integrated circuit or device is provided. The method includes monitoring on-chip temperatures, power dissipation, and performance of device layers. The method includes comparing on-chip temperatures to thermal thresholds, on-chip power dissipation to power thresholds and on-chip performance to performance thresholds. Also, the method includes analyzing interactions between temperatures, power, and performance of different device layers within the multi-dimensional integrated circuits. The method includes activating layer-specific thermal and power management within performance constraints on one or more device layers through actuators in the corresponding device layers, depending on the severity of heating.
摘要翻译：提供了一种多维集成电路或器件中的动态热管理方法。该方法包括监测片上温度，功耗和器件层的性能。该方法包括将片上温度与热阈值进行比较，将片上功耗降至功率阈值，并将片上性能与性能阈值进行比较。此外，该方法包括分析多维集成电路内不同器件层的温度，功率和性能之间的相互作用。该方法包括根据加热的严重程度，通过相应设备层中的致动器在一个或多个设备层上的性能约束内激活层特定的热和功率管理。

19. 发明授权

US07447923B2 Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power 失效
标题翻译：用于互相激活微处理器资源以控制最大功率的系统和方法
公开(公告)号：US07447923B2
公开(公告)日：2008-11-04
申请号：US11207333
申请日：2005-08-19
申请人： Pradip Bose , Alper Buyuktosunoglu , Zhigang Hu , Hans Mikael Jacobson , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Zhigang Hu , Hans Mikael Jacobson , Vijayalakshmi Srinivasan , Victor Zyuban
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/30145 , G06F9/382 , G06F9/3836 , G06F9/3842 , G06F9/3867 , Y02D10/171 , Y02D10/24
摘要： A device for controlling power parameters in a microprocessor includes a resource activation control unit for controlling the maximum power of the microprocessor and two or more resources. The resource activation control unit controls the activation of the resources such that the consumed and dissipated power of the microprocessor does not exceed a power bound which is configurable to a predetermined value below the maximum power.
摘要翻译：用于控制微处理器中的功率参数的装置包括用于控制微处理器的最大功率和两个或更多个资源的资源激活控制单元。资源激活控制单元控制资源的激活，使得微处理器的消耗和耗散功率不超过可配置为低于最大功率的预定值的功率限制。

20. 发明授权

US07392366B2 Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches 有权
标题翻译：多线程处理器中的自适应提取门控，提取控制和控制提取的方法
公开(公告)号：US07392366B2
公开(公告)日：2008-06-24
申请号：US11228781
申请日：2005-09-16
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard J. Eickemeyer , Lee E. Eisen , Philip G. Emma , John B. Griswell , Zhigang Hu , Hung Q. Le , Douglas R. Logan , Balaram Sinharoy
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard J. Eickemeyer , Lee E. Eisen , Philip G. Emma , John B. Griswell , Zhigang Hu , Hung Q. Le , Douglas R. Logan , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3867
摘要： A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.
摘要翻译：多线程处理器，用于多线程处理器的获取控制以及在多线程处理器中获取的方法。监视处理器事件和使用（EU）符号，用于指示管道执行线程状态的下游管道条件。对于不能接收获取的高速缓存内容的任何线程，例如由于线程已满或停顿，跳过指令高速缓存提取。此外，可以针对相同的线程选择连续的提取，例如在分支误预测中。因此，处理器避免浪费电力不必要的或放置保持器提取。

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