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11. 发明申请

US20100123193A1 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 审中-公开
标题翻译：半导体元件及其制造方法
公开(公告)号：US20100123193A1
公开(公告)日：2010-05-20
申请号：US12271092
申请日：2008-11-14
申请人： Peter A. Burke , Duane B. Barber , Brian Pratt
发明人： Peter A. Burke , Duane B. Barber , Brian Pratt
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L27/088 , H01L21/823487
摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.
摘要翻译：包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。在器件区域的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

12. 发明申请

US20110127603A1 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US20110127603A1
公开(公告)日：2011-06-02
申请号：US13022628
申请日：2011-02-07
申请人： Peter A. Burke , Duane B. Barber , Brian Pratt
发明人： Peter A. Burke , Duane B. Barber , Brian Pratt
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66727 , H01L29/407 , H01L29/41766 , H01L29/42376 , H01L29/456 , H01L29/4933 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813
摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.
摘要翻译：包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。屏蔽电极形成在与它们的地板相邻的器件沟槽的部分中。在器件区域中的沟槽的侧壁上形成栅极电介质材料，并且在屏蔽电极之间形成栅电极并与屏蔽电极电绝缘。器件区域中的沟槽中的栅电极连接到栅极接触区域中的沟槽中的栅电极。器件区域的沟槽中的屏蔽电极与端接区域中的屏蔽电极相连。

13. 发明授权

US08410578B2 Method of manufacturing a semiconductor component and structure 有权
标题翻译：制造半导体元件和结构的方法
公开(公告)号：US08410578B2
公开(公告)日：2013-04-02
申请号：US12962579
申请日：2010-12-07
申请人： Sallie Hose , Peter A. Burke , Li Jiang , Sudhama C. Shastri
发明人： Sallie Hose , Peter A. Burke , Li Jiang , Sudhama C. Shastri
IPC分类号： H01L29/94 , H01L21/02 , H01L21/768
CPC分类号： H01L23/5227 , H01L23/5223 , H01L23/5228 , H01L23/53238 , H01L24/05 , H01L27/0629 , H01L28/10 , H01L28/24 , H01L28/40 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/12035 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated passive device. In accordance with embodiments, the monolithically integrated passive device includes an inductor formed from damascene structures.
摘要翻译：一种半导体元件及其制造方法，该半导体元件包括单片集成无源器件。根据实施例，单片集成无源器件包括由镶嵌结构形成的电感器。

14. 发明申请

US20110052449A1 DEVICE FOR AERATING A REGION AFTER INJECTION WITH VAPORIZED HYDROGEN PEROXIDE 有权
标题翻译：用过氧化氢过滤注入一个地区的装置
公开(公告)号：US20110052449A1
公开(公告)日：2011-03-03
申请号：US12939246
申请日：2010-11-04
申请人： Michael A. Centanni , Peter A. Burke
发明人： Michael A. Centanni , Peter A. Burke
IPC分类号： A62B7/08
CPC分类号： A61L2/208 , A61L2/202 , A61L2/206 , A61L9/015 , A61L2202/13
摘要： A method and apparatus for aerating a region exposed to a gaseous/vaporous sterilant. A catalytic destroyer and a reactive chemical unit are used to reduce the concentration of the gaseous/vaporous sterilant within the region. The reactive chemical unit includes a chemistry that is chemically reactive with the gaseous/vaporous sterilant. In one embodiment, the gaseous/vaporous sterilant is vaporized hydrogen peroxide and the chemistry of the reactive chemical unit includes thiosulfate and iodide.
摘要翻译：用于对暴露于气体/蒸气灭菌剂的区域进行曝气的方法和装置。催化破坏剂和反应性化学单元用于降低该区域内气态/蒸气灭菌剂的浓度。反应性化学单元包括与气态/蒸气灭菌剂化学反应的化学物质。在一个实施方案中，气态/蒸气灭菌剂是蒸发的过氧化氢，并且反应性化学单元的化学性质包括硫代硫酸盐和碘化物。

15. 发明授权

US07829426B2 Semiconductor component and method of manufacture 有权
标题翻译：半导体元件及制造方法
公开(公告)号：US07829426B2
公开(公告)日：2010-11-09
申请号：US12549100
申请日：2009-08-27
申请人： Peter A. Burke , Sallie Hose , Sudhama C. Shastri
发明人： Peter A. Burke , Sallie Hose , Sudhama C. Shastri
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L21/76801 , H01L21/76807 , H01L21/76846 , H01L23/5227 , H01L23/5228 , H01L23/53238 , H01L28/20 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.
摘要翻译：一种包括集成无源器件的半导体部件和用于制造半导体部件的方法。在衬底上方制造垂直集成的无源器件。根据一个实施例，在基板上方的第一电平中制造电阻器，在垂直于第一电平的第二电平上制造电容器，并且在垂直于第二电平的第三电平上制造铜电感器水平。电容器有铝板。根据另一个实施例，在基板上方的第一电平中制造电阻器，在垂直于第一电平的第二电平上制造铜电感器，并且制造在垂直于第二电平的第三电平的电容器水平。电容器可以具有铝板，或者铜电感器的一部分可以用作其板之一。

16. 发明授权

US07824946B1 Isolated metal plug process for use in fabricating carbon nanotube memory cells 有权
标题翻译：用于制造碳纳米管记忆单元的隔离金属塞工艺
公开(公告)号：US07824946B1
公开(公告)日：2010-11-02
申请号：US11429069
申请日：2006-05-05
申请人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Claude L. Bertin , Thomas Rueckes
发明人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Claude L. Bertin , Thomas Rueckes
IPC分类号： H01L21/00 , H01L21/64
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译：本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。纳米管横杆元件布置成跨越下室。第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。

17. 发明申请

US20100200993A1 DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES 有权
标题翻译：用于增加铜互连结构中电磁寿命的电介质障碍层
公开(公告)号：US20100200993A1
公开(公告)日：2010-08-12
申请号：US12764004
申请日：2010-04-20
申请人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
发明人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
IPC分类号： H01L23/532 , H01L21/31
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76826 , H01L21/76834 , H01L21/76883
摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.
摘要翻译：本发明的实施例包括具有增加的电迁移寿命的铜互连结构。这种结构可以包括其上形成有铜层的半导体衬底。在铜层上形成介电阻挡层叠体。电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改善的对铜的粘合性，并且两个部分形成为具有耐铜扩散性。本发明还包括用于构造这种结构的几个实施例。可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

18. 发明授权

US07666701B1 Isolated metal plug process for use in fabricating carbon nanotube memory cells 有权
公开(公告)号：US07666701B1
公开(公告)日：2010-02-23
申请号：US11429069
申请日：2006-05-05
申请人： Richard J. Carter , Peter A. Burke , Verne C. Hornback
发明人： Richard J. Carter , Peter A. Burke , Verne C. Hornback
IPC分类号： H01L21/00 , H01L21/64
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.

19. 发明授权

US07602027B2 Semiconductor component and method of manufacture 有权
公开(公告)号：US07602027B2
公开(公告)日：2009-10-13
申请号：US11618363
申请日：2006-12-29
申请人： Peter A. Burke , Sallie Hose , Sudhama C. Shastri
发明人： Peter A. Burke , Sallie Hose , Sudhama C. Shastri
IPC分类号： H01L27/13
CPC分类号： H01L23/5223 , H01L21/76801 , H01L21/76807 , H01L21/76846 , H01L23/5227 , H01L23/5228 , H01L23/53238 , H01L28/20 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

20. 发明授权

US07427563B2 Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures 有权
标题翻译：用作半导体沟槽和通孔结构中的铜阻挡层的介电阻挡膜
公开(公告)号：US07427563B2
公开(公告)日：2008-09-23
申请号：US11131003
申请日：2005-05-16
申请人： Hong-Qiang Lu , Peter A. Burke , Wilbur G. Catabay
发明人： Hong-Qiang Lu , Peter A. Burke , Wilbur G. Catabay
IPC分类号： H01L21/4763
CPC分类号： H01L21/02211 , H01L21/02126 , H01L21/02167 , H01L21/02315 , H01L21/02348 , H01L21/02351 , H01L21/3121 , H01L21/76807 , H01L21/76826 , H01L21/76831 , H01L21/76832 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.
摘要翻译：本发明涉及改进的介电铜阻挡层和相关互连结构。一种结构包括具有铜线的半导体衬底。在下面的铜线上形成由硅和碳中的至少一种形成的绝缘层。在绝缘层中形成开口以露出铜线的一部分。绝缘层中的开口的内表面具有形成在其上的电介质阻挡层，以防止铜扩散到绝缘层中。形成铜塞以填充开口并与下面的铜互连结构电接触。本发明的方面还包括用于形成电介质铜阻挡层和将铜互连连接到下面的铜线的方法。

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