专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20060146622A1 Performing memory built-in-self-test (MBIST) 有权
标题翻译：执行内存自检（MBIST）
公开(公告)号：US20060146622A1
公开(公告)日：2006-07-06
申请号：US11283499
申请日：2005-11-18
申请人： Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
发明人： Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
IPC分类号： G11C29/00
CPC分类号： G01R31/3187 , G01R31/31724 , G01R31/318519 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/20 , G11C2029/0401 , G11C2029/0405 , G11C2029/3602 , G11C2029/5604
摘要： Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.
摘要翻译：公开了可编程存储器内置的自检（MBIST）方法，装置和系统。所公开的技术的示例性实施例可以用于例如在制造测试期间测试位于集成电路上的一个或多个存储器。

12. 发明授权

US06456961B1 Method and apparatus for creating testable circuit designs having embedded cores 有权
标题翻译：用于创建具有嵌入式核心的可测试电路设计的方法和装置
公开(公告)号：US06456961B1
公开(公告)日：2002-09-24
申请号：US09302699
申请日：1999-04-30
申请人： Srinivas Patil , Wu-Tung Cheng , Paul J. Reuter
发明人： Srinivas Patil , Wu-Tung Cheng , Paul J. Reuter
IPC分类号： G06F1750
CPC分类号： G01R31/318505
摘要： A computer-implemented method and apparatus for creating a testable circuit design that includes one or more embedded cores. The method includes identifying an embedded core within the circuit design; associating certain pins of the embedded core with pins of the circuit design; and inserting into the circuit design access circuitry coupling the certain connection pins of the embedded core to the associated pins of the circuit design. The method further includes providing test vectors for the embedded core; and generating test vectors for the circuit design by mapping the core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design. The cores within the circuit design can then be tested after manufacture by applying the design test vectors to the circuit design.
摘要翻译：一种用于创建包括一个或多个嵌入式核心的可测试电路设计的计算机实现的方法和装置。该方法包括识别电路设计内的嵌入式核心; 将嵌入式核心的某些引脚与电路设计的引脚相关联; 并将插入到嵌入式芯的某些连接引脚的电路设计访问电路插入电路设计的相关引脚。该方法还包括提供用于嵌入式核心的测试向量; 以及通过将适用于嵌入式核心的某些引脚的核心测试向量映射到电路设计的相关引脚来生成用于电路设计的测试向量。然后可以通过将设计测试矢量应用于电路设计，然后在制造后对电路设计中的核心进行测试。

13. 发明授权

US08280688B2 Compactor independent direct diagnosis of test hardware 有权
标题翻译：压缩机独立直接诊断测试硬件
公开(公告)号：US08280688B2
公开(公告)日：2012-10-02
申请号：US12790049
申请日：2010-05-28
申请人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
发明人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
IPC分类号： G06F11/30 , G06F11/00
CPC分类号： G01R31/318547 , G06F11/267 , G06F11/27
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received comprising entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在一个示例性实施例中，接收到故障日志，其包括指示对链模式的压缩测试响应的条目和对扫描模式的压缩测试响应。至少部分地基于指示压缩的测试对链模式的测试响应的一个或多个条目来识别被测电路中的有缺陷的扫描链。至少部分地基于指示对扫描模式的压缩测试响应的一个或多个条目来识别故障扫描链中的一个或多个错误的扫描小区候选。可以报告一个或多个识别的扫描单元候选。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样，还提供了存储通过任何所公开的方法识别的故障候选列表的计算机可读介质。

14. 发明授权

US07239978B2 Compactor independent fault diagnosis 有权
标题翻译：压实机独立故障诊断
公开(公告)号：US07239978B2
公开(公告)日：2007-07-03
申请号：US10925230
申请日：2004-08-23
申请人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
发明人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
IPC分类号： G06F11/30 , G01R31/28
CPC分类号： G01R31/318547 , G06F11/267
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In certain disclosed embodiments, methods for diagnosing faults from compressed test responses are provided. For example, in one exemplary embodiment, a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test is received. A transformation function performed by the compactor to the test responses captured in the circuit-under-test is determined. A diagnostic procedure for evaluating uncompressed test responses is modified into a modified diagnostic procedure that incorporates the transformation function therein. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media comprising lists of fault candidates identified by any of the disclosed methods or circuit descriptions created or modified by the disclosed methods are provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在某些公开的实施例中，提供了用于从压缩测试响应诊断故障的方法。例如，在一个示例性实施例中，接收至少部分基于扫描的测试电路和压实器的电路描述，用于压缩在待测电路中捕获的测试响应。确定由压实机对被测电路中捕获的测试响应执行的变换功能。用于评估未压缩测试响应的诊断程序被修改为并入其中的变换功能的修改的诊断过程。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样地，提供了包括通过由所公开的方法创建或修改的任何公开的方法或电路描述所识别的故障候选列表的计算机可读介质。

15. 发明授权

US09086459B2 Detection and diagnosis of scan cell internal defects 有权
标题翻译：检测和诊断扫描单元内部缺陷
公开(公告)号：US09086459B2
公开(公告)日：2015-07-21
申请号：US12918986
申请日：2009-02-23
申请人： Ruifeng Guo , Liyang Lai , Yu Huang , Wu-Tung Cheng
发明人： Ruifeng Guo , Liyang Lai , Yu Huang , Wu-Tung Cheng
IPC分类号： G01R31/28 , G01R31/3185 , G01R35/00
CPC分类号： G01R31/318583 , G01R31/318541 , G01R35/00
摘要： A diagnosis technique to improve scan cell internal defect diagnostic resolution using scan cell internal fault models.
摘要翻译：使用扫描单元内部故障模型提高扫描单元内部缺陷诊断分辨率的诊断技术。

16. 发明授权

US08261142B2 Generating test sets for diagnosing scan chain failures 有权
标题翻译：生成用于诊断扫描链失败的测试集
公开(公告)号：US08261142B2
公开(公告)日：2012-09-04
申请号：US12074162
申请日：2008-02-29
申请人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
发明人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318525 , G01R31/31853 , G01R31/318533 , G01R31/318544 , G01R31/318569
摘要： Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.
摘要翻译：所公开技术的实施例包括可用于改进扫描链测试模式生成和扫描链故障诊断解析的基于软件的技术。例如，某些实施例可用于产生能够将扫描链缺陷隔离成单个扫描单元的高质量链诊断测试图案。这样的实施例可以用于产生“完整”测试集，即，能够将故障扫描链中的任何扫描链缺陷分离到单个扫描单元的一组链诊断测试模式。

17. 发明申请

US20100306606A1 COMPACTOR INDEPENDENT DIRECT DIAGNOSIS OF TEST HARDWARE 有权
标题翻译：测试硬件的独立直接诊断测试
公开(公告)号：US20100306606A1
公开(公告)日：2010-12-02
申请号：US12790049
申请日：2010-05-28
申请人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
发明人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547 , G06F11/267 , G06F11/27
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received comprising entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在一个示例性实施例中，接收到故障日志，其包括指示对链模式的压缩测试响应的条目和对扫描模式的压缩测试响应。至少部分地基于指示压缩的测试对链模式的测试响应的一个或多个条目来识别被测电路中的有缺陷的扫描链。至少部分地基于指示对扫描模式的压缩测试响应的一个或多个条目来识别故障扫描链中的一个或多个错误的扫描小区候选。可以报告一个或多个识别的扫描单元候选。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样，还提供了存储通过任何所公开的方法识别的故障候选列表的计算机可读介质。

18. 发明授权

US07788561B2 Diagnosing mixed scan chain and system logic defects 有权
标题翻译：诊断混合扫描链和系统逻辑缺陷
公开(公告)号：US07788561B2
公开(公告)日：2010-08-31
申请号：US11838858
申请日：2007-08-14
申请人： Yu Huang , Wu-Tung Cheng , Ruifeng Guo
发明人： Yu Huang , Wu-Tung Cheng , Ruifeng Guo
IPC分类号： G01R31/28
CPC分类号： G01R31/318569
摘要： Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.
摘要翻译：本文公开的技术可用于诊断具有扫描链和系统逻辑缺陷的裸片上的缺陷，包括在系统逻辑中存在一个或多个故障潜在地掩盖扫描链中的一个或多个故障的可检测性的情况下（或频道），反之亦然。至少一些实施例采用迭代方法，其中识别出至少一些扫描链故障，这些链故障用于识别系统逻辑故障，然后使用系统逻辑故障来识别附加链故障，反之亦然。失败的位可被划分为至少两组：确定为由系统逻辑故障引起的故障位，以及确定为可能由链缺陷，系统逻辑缺陷或两种类型的缺陷的复合效应引起的故障位。

19. 发明申请

US20090235134A1 TEST PATTERN GENERATION FOR DIAGNOSING SCAN CHAIN FAILURES 有权
标题翻译：用于诊断扫描链失败的测试图形生成
公开(公告)号：US20090235134A1
公开(公告)日：2009-09-17
申请号：US12471227
申请日：2009-05-22
申请人： Ruifeng Guo , Wu-Tung Cheng , Yu Huang
发明人： Ruifeng Guo , Wu-Tung Cheng , Yu Huang
IPC分类号： G01R31/3177 , G06F11/25 , G06F15/16
CPC分类号： G01R31/318544
摘要： Embodiments of the disclosed technology comprise techniques that can be used to generate scan chain test patterns and improve scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. At least some embodiments can be used to locate faults over multiple capture cycles in the scan chain.
摘要翻译：所公开技术的实施例包括可用于产生扫描链测试模式并提高扫描链故障诊断分辨率的技术。例如，某些实施例可用于产生能够将扫描链缺陷隔离成单个扫描单元的高质量链诊断测试图案。至少一些实施例可用于在扫描链中的多个捕获周期上定位故障。

20. 发明申请

US20080215943A1 Generating test sets for diagnosing scan chain failures 有权
标题翻译：生成用于诊断扫描链故障的测试集
公开(公告)号：US20080215943A1
公开(公告)日：2008-09-04
申请号：US12074162
申请日：2008-02-29
申请人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
发明人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318525 , G01R31/31853 , G01R31/318533 , G01R31/318544 , G01R31/318569
摘要： Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.
摘要翻译：所公开的技术的实施例包括可用于改进扫描链测试模式生成和扫描链故障诊断解析的基于软件的技术。例如，某些实施例可用于产生能够将扫描链缺陷隔离成单个扫描单元的高质量链诊断测试图案。这样的实施例可用于产生“完整”测试集，即，能够将故障扫描链中的任何扫描链缺陷分离到单个扫描单元的一组链诊断测试模式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式